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Commit 93583e17 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: math-emu: Fix BC1{EQ,NE}Z emulation 



The conditions for branching when emulating the BC1EQZ & BC1NEZ
instructions were backwards, leading to each of those instructions being
treated as the other. Fix this by reversing the conditions, and clear up
the code a little for readability & checkpatch.

Fixes: c909ca71 ("MIPS: math-emu: Emulate missing BC1{EQ,NE}Z instructions")
Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/13150/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent ed47e153

arch/mips/math-emu/cp1emu.c

+6 −5
Original line number Diff line number Diff line
@@ -973,9 +973,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
		struct mm_decoded_insn dec_insn, void *__user *fault_addr)

{

	unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;

	unsigned int cond, cbit;

	unsigned int cond, cbit, bit0;

	mips_instruction ir;

	int likely, pc_inc;

	union fpureg *fpr;

	u32 __user *wva;

	u64 __user *dva;

	u32 wval;
@@ -1187,14 +1188,14 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 
				return SIGILL;



			cond = likely = 0;

			fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];

			bit0 = get_fpr32(fpr, 0) & 0x1;

			switch (MIPSInst_RS(ir)) {

			case bc1eqz_op:

				if (get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1)

				    cond = 1;

				cond = bit0 == 0;

				break;

			case bc1nez_op:

				if (!(get_fpr32(&current->thread.fpu.fpr[MIPSInst_RT(ir)], 0) & 0x1))

				    cond = 1;

				cond = bit0 != 0;

				break;

			}

			goto branch_common;