Merge branch 'x86/irq' into perfcounters/core (92bf73e9) · Commits · e / devices / android_kernel_teracube_emerald

Makefile

+1 −1

Original line number	Diff line number	Diff line
		VERSION = 2
		PATCHLEVEL = 6
		SUBLEVEL = 28
		EXTRAVERSION = -rc7
		EXTRAVERSION = -rc8
		NAME = Erotic Pickled Herring

		# DOCUMENTATION

arch/arm/include/asm/bitops.h

+10 −6

Original line number	Diff line number	Diff line
		@@ -237,6 +237,7 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
		#if __LINUX_ARM_ARCH__ < 5

		#include <asm-generic/bitops/ffz.h>
		#include <asm-generic/bitops/__fls.h>
		#include <asm-generic/bitops/__ffs.h>
		#include <asm-generic/bitops/fls.h>
		#include <asm-generic/bitops/ffs.h>
		@@ -277,16 +278,19 @@ static inline int constant_fls(int x)
		* the clz instruction for much better code efficiency.
		*/

		#define __fls(x) \
		( __builtin_constant_p(x) ? constant_fls(x) : \
		({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )

		/* Implement fls() in C so that 64-bit args are suitably truncated */
		static inline int fls(int x)
		{
		return __fls(x);
		int ret;

		if (__builtin_constant_p(x))
		return constant_fls(x);

		asm("clz\t%0, %1" : "=r" (ret) : "r" (x) : "cc");
		ret = 32 - ret;
		return ret;
		}

		#define __fls(x) (fls(x) - 1)
		#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
		#define __ffs(x) (ffs(x) - 1)
		#define ffz(x) __ffs( ~(x) )

arch/arm/include/asm/processor.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -23,7 +23,7 @@
		#include <asm/types.h>

		#ifdef __KERNEL__
		#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \
		#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \
		TASK_SIZE : TASK_SIZE_26)
		#define STACK_TOP_MAX TASK_SIZE
		#endif

arch/arm/mach-omap1/io.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -128,7 +128,7 @@ void __init omap1_map_common_io(void)
		* Common low-level hardware init for omap1. This should only get called from
		* board specific init.
		*/
		void __init omap1_init_common_hw()
		void __init omap1_init_common_hw(void)
		{
		/* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
		* on a Posted Write in the TIPB Bridge".

arch/arm/mm/alignment.c

+23 −3

Original line number	Diff line number	Diff line
		@@ -70,6 +70,10 @@ static unsigned long ai_dword;
		static unsigned long ai_multi;
		static int ai_usermode;

		#define UM_WARN (1 << 0)
		#define UM_FIXUP (1 << 1)
		#define UM_SIGNAL (1 << 2)

		#ifdef CONFIG_PROC_FS
		static const char *usermode_action[] = {
		"ignored",
		@@ -754,7 +758,7 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
		user:
		ai_user += 1;

		if (ai_usermode & 1)
		if (ai_usermode & UM_WARN)
		printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
		"Address=0x%08lx FSR 0x%03x\n", current->comm,
		task_pid_nr(current), instrptr,
		@@ -762,10 +766,10 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
		thumb_mode(regs) ? tinstr : instr,
		addr, fsr);

		if (ai_usermode & 2)
		if (ai_usermode & UM_FIXUP)
		goto fixup;

		if (ai_usermode & 4)
		if (ai_usermode & UM_SIGNAL)
		force_sig(SIGBUS, current);
		else
		set_cr(cr_no_alignment);
		@@ -796,6 +800,22 @@ static int __init alignment_init(void)
		res->write_proc = proc_alignment_write;
		#endif

		/*
		* ARMv6 and later CPUs can perform unaligned accesses for
		* most single load and store instructions up to word size.
		* LDM, STM, LDRD and STRD still need to be handled.
		*
		* Ignoring the alignment fault is not an option on these
		* CPUs since we spin re-faulting the instruction without
		* making any progress.
		*/
		if (cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U)) {
		cr_alignment &= ~CR_A;
		cr_no_alignment &= ~CR_A;
		set_cr(cr_alignment);
		ai_usermode = UM_FIXUP;
		}

		hook_fault_code(1, do_alignment, SIGILL, "alignment exception");
		hook_fault_code(3, do_alignment, SIGILL, "alignment exception");