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Commit 92b05d82 authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amd/powerplay: enable clock gating for Fiji. 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
parent 6cec2655

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

+8 −1
Original line number Diff line number Diff line
@@ -917,7 +917,14 @@ static int fiji_start_smu(struct pp_smumgr *smumgr) 
	}



	/* To initialize all clock gating before RLC loaded and running.*/

	/*PECI_InitClockGating(peci);*/

	cgs_set_clockgating_state(smumgr->device,

			AMD_IP_BLOCK_TYPE_GFX, AMD_CG_STATE_GATE);

	cgs_set_clockgating_state(smumgr->device,

			AMD_IP_BLOCK_TYPE_GMC, AMD_CG_STATE_GATE);

	cgs_set_clockgating_state(smumgr->device,

			AMD_IP_BLOCK_TYPE_SDMA, AMD_CG_STATE_GATE);

	cgs_set_clockgating_state(smumgr->device,

			AMD_IP_BLOCK_TYPE_COMMON, AMD_CG_STATE_GATE);



	/* Setup SoftRegsStart here for register lookup in case

	 * DummyBackEnd is used and ProcessFirmwareHeader is not executed