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Commit 9287b95e authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
Browse files

Merge remote-tracking branch 'scott/next' into next 

Scott writes:

Highlights include e6500 hardware threading support, an e6500 TLB erratum
workaround, corenet error reporting, support for a new board, and some
minor fixes.
parents ea668936 78eb9094

Documentation/devicetree/bindings/powerpc/fsl/board.txt

+16 −0
Original line number Diff line number Diff line
@@ -84,3 +84,19 @@ Example: 
		compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";

		reg = <0x66>;

	};



* Freescale on-board CPLD



Some Freescale boards like T1040RDB have an on board CPLD connected.



Required properties:

- compatible: Should be a board-specific string like "fsl,<board>-cpld"

  Example:

	"fsl,t1040rdb-cpld", "fsl,t1042rdb-cpld", "fsl,t1042rdb_pi-cpld"

- reg: should describe CPLD registers



Example:

	cpld@3,0 {

		compatible = "fsl,t1040rdb-cpld";

		reg = <3 0 0x300>;

	};

arch/powerpc/boot/dts/t2080rdb.dts

0 → 100644
+57 −0
Original line number Diff line number Diff line 
/*

 * T2080PCIe-RDB Board Device Tree Source

 *

 * Copyright 2014 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *	 notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *	 notice, this list of conditions and the following disclaimer in the

 *	 documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *	 names of its contributors may be used to endorse or promote products

 *	 derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/include/ "fsl/t208xsi-pre.dtsi"

/include/ "t208xrdb.dtsi"



/ {

	model = "fsl,T2080RDB";

	compatible = "fsl,T2080RDB";

	#address-cells = <2>;

	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	rio: rapidio@ffe0c0000 {

		reg = <0xf 0xfe0c0000 0 0x11000>;



		port1 {

			ranges = <0 0 0xc 0x20000000 0 0x10000000>;

		};

		port2 {

			ranges = <0 0 0xc 0x30000000 0 0x10000000>;

		};

	};

};



/include/ "fsl/t2080si-post.dtsi"

arch/powerpc/boot/dts/t208xrdb.dtsi

0 → 100644
+184 −0
Original line number Diff line number Diff line 
/*

 * T2080PCIe-RDB Board Device Tree Source

 *

 * Copyright 2014 Freescale Semiconductor Inc.

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions are met:

 *     * Redistributions of source code must retain the above copyright

 *	 notice, this list of conditions and the following disclaimer.

 *     * Redistributions in binary form must reproduce the above copyright

 *	 notice, this list of conditions and the following disclaimer in the

 *	 documentation and/or other materials provided with the distribution.

 *     * Neither the name of Freescale Semiconductor nor the

 *	 names of its contributors may be used to endorse or promote products

 *	 derived from this software without specific prior written permission.

 *

 *

 * ALTERNATIVELY, this software may be distributed under the terms of the

 * GNU General Public License ("GPL") as published by the Free Software

 * Foundation, either version 2 of that License or (at your option) any

 * later version.

 *

 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY

 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY

 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES

 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;

 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND

 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS

 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */



/ {

	model = "fsl,T2080RDB";

	compatible = "fsl,T2080RDB";

	#address-cells = <2>;

	#size-cells = <2>;

	interrupt-parent = <&mpic>;



	ifc: localbus@ffe124000 {

		reg = <0xf 0xfe124000 0 0x2000>;

		ranges = <0 0 0xf 0xe8000000 0x08000000

			  2 0 0xf 0xff800000 0x00010000

			  3 0 0xf 0xffdf0000 0x00008000>;



		nor@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0x0 0x0 0x8000000>;



			bank-width = <2>;

			device-width = <1>;

		};



		nand@1,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,ifc-nand";

			reg = <0x2 0x0 0x10000>;

		};



		boardctrl: board-control@2,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,t2080-cpld";

			reg = <3 0 0x300>;

			ranges = <0 3 0 0x300>;

		};

	};



	memory {

		device_type = "memory";

	};



	dcsr: dcsr@f00000000 {

		ranges = <0x00000000 0xf 0x00000000 0x01072000>;

	};



	soc: soc@ffe000000 {

		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;

		reg = <0xf 0xfe000000 0 0x00001000>;

		spi@110000 {

			flash@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				compatible = "micron,n25q512a";

				reg = <0>;

				spi-max-frequency = <10000000>; /* input clock */

			};

		};



		i2c@118000 {

			adt7481@4c {

				compatible = "adi,adt7481";

				reg = <0x4c>;

			};



			rtc@68 {

				compatible = "dallas,ds1339";

				reg = <0x68>;

				interrupts = <0x1 0x1 0 0>;

			};



			eeprom@50 {

				compatible = "atmel,24c256";

				reg = <0x50>;

			};

		};



		i2c@118100 {

			pca9546@77 {

				compatible = "nxp,pca9546";

				reg = <0x77>;

			};

		};



		sdhc@114000 {

			voltage-ranges = <1800 1800 3300 3300>;

		};

	};



	pci0: pcie@ffe240000 {

		reg = <0xf 0xfe240000 0 0x10000>;

		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000

			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;

		pcie@0 {

			ranges = <0x02000000 0 0xe0000000

				  0x02000000 0 0xe0000000

				  0 0x20000000



				  0x01000000 0 0x00000000

				  0x01000000 0 0x00000000

				  0 0x00010000>;

		};

	};



	pci1: pcie@ffe250000 {

		reg = <0xf 0xfe250000 0 0x10000>;

		ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;

		pcie@0 {

			ranges = <0x02000000 0 0xe0000000

				  0x02000000 0 0xe0000000

				  0 0x20000000



				  0x01000000 0 0x00000000

				  0x01000000 0 0x00000000

				  0 0x00010000>;

		};

	};



	pci2: pcie@ffe260000 {

		reg = <0xf 0xfe260000 0 0x1000>;

		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000

			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;

		pcie@0 {

			ranges = <0x02000000 0 0xe0000000

				  0x02000000 0 0xe0000000

				  0 0x20000000



				  0x01000000 0 0x00000000

				  0x01000000 0 0x00000000

				  0 0x00010000>;

		};

	};



	pci3: pcie@ffe270000 {

		reg = <0xf 0xfe270000 0 0x10000>;

		ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000

			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;

		pcie@0 {

			ranges = <0x02000000 0 0xe0000000

				  0x02000000 0 0xe0000000

				  0 0x20000000



				  0x01000000 0 0x00000000

				  0x01000000 0 0x00000000

				  0 0x00010000>;

		};

	};

};

arch/powerpc/configs/corenet32_smp_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -180,3 +180,4 @@ CONFIG_CRYPTO_SHA512=y 
CONFIG_CRYPTO_AES=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

CONFIG_CRYPTO_DEV_FSL_CAAM=y

CONFIG_FSL_CORENET_CF=y

arch/powerpc/configs/corenet64_smp_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -179,3 +179,4 @@ CONFIG_CRYPTO_SHA256=y 
CONFIG_CRYPTO_SHA512=y

# CONFIG_CRYPTO_ANSI_CPRNG is not set

CONFIG_CRYPTO_DEV_FSL_CAAM=y

CONFIG_FSL_CORENET_CF=y