Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 920dfd82 authored by Chang Rebecca Swee Fun's avatar Chang Rebecca Swee Fun Committed by Linus Walleij
Browse files

gpio: sch: Consolidate similar algorithms 



Consolidating similar algorithms into common functions to make
GPIO SCH simpler and manageable.

Signed-off-by: default avatarChang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
Reviewed-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Reviewed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 68d77d51

drivers/gpio/gpio-sch.c

+29 −54
Original line number Original line Diff line number Diff line
@@ -41,7 +41,7 @@ struct sch_gpio { 
	unsigned short resume_base;

	unsigned short resume_base;

};

};





#define to_sch_gpio(c)	container_of(c, struct sch_gpio, chip)

#define to_sch_gpio(gc)	container_of(gc, struct sch_gpio, chip)





static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,

static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,

				unsigned reg)

				unsigned reg)
@@ -63,75 +63,59 @@ static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio) 
	return gpio % 8;

	return gpio % 8;

}

}





static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)

static int sch_gpio_reg_get(struct gpio_chip *gc, unsigned gpio, unsigned reg)

{

{

	struct sch_gpio *sch = to_sch_gpio(gc);

	unsigned short offset, bit;

	unsigned short offset, bit;

	u8 enable;

	u8 reg_val;



	spin_lock(&sch->lock);





	offset = sch_gpio_offset(sch, gpio, GEN);

	offset = sch_gpio_offset(sch, gpio, reg);

	bit = sch_gpio_bit(sch, gpio);

	bit = sch_gpio_bit(sch, gpio);





	enable = inb(sch->iobase + offset);

	reg_val = !!(inb(sch->iobase + offset) & BIT(bit));

	if (!(enable & (1 << bit)))

		outb(enable | (1 << bit), sch->iobase + offset);





	spin_unlock(&sch->lock);

	return reg_val;

}

}





static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned  gpio_num)

static void sch_gpio_reg_set(struct gpio_chip *gc, unsigned gpio, unsigned reg,

			     int val)

{

{

	struct sch_gpio *sch = to_sch_gpio(gc);

	struct sch_gpio *sch = to_sch_gpio(gc);

	u8 curr_dirs;

	unsigned short offset, bit;

	unsigned short offset, bit;

	u8 reg_val;





	spin_lock(&sch->lock);

	offset = sch_gpio_offset(sch, gpio, reg);

	bit = sch_gpio_bit(sch, gpio);





	offset = sch_gpio_offset(sch, gpio_num, GIO);

	reg_val = inb(sch->iobase + offset);

	bit = sch_gpio_bit(sch, gpio_num);





	curr_dirs = inb(sch->iobase + offset);

	if (val)

		outb(reg_val | BIT(bit), sch->iobase + offset);

	else

		outb((reg_val & ~BIT(bit)), sch->iobase + offset);

}





	if (!(curr_dirs & (1 << bit)))

static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)

		outb(curr_dirs | (1 << bit), sch->iobase + offset);

{

	struct sch_gpio *sch = to_sch_gpio(gc);





	spin_lock(&sch->lock);

	sch_gpio_reg_set(gc, gpio_num, GIO, 1);

	spin_unlock(&sch->lock);

	spin_unlock(&sch->lock);

	return 0;

	return 0;

}

}





static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)

static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)

{

{

	struct sch_gpio *sch = to_sch_gpio(gc);

	return sch_gpio_reg_get(gc, gpio_num, GLV);

	int res;

	unsigned short offset, bit;



	offset = sch_gpio_offset(sch, gpio_num, GLV);

	bit = sch_gpio_bit(sch, gpio_num);



	res = !!(inb(sch->iobase + offset) & (1 << bit));



	return res;

}

}





static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)

static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)

{

{

	struct sch_gpio *sch = to_sch_gpio(gc);

	struct sch_gpio *sch = to_sch_gpio(gc);

	u8 curr_vals;

	unsigned short offset, bit;





	spin_lock(&sch->lock);

	spin_lock(&sch->lock);



	sch_gpio_reg_set(gc, gpio_num, GLV, val);

	offset = sch_gpio_offset(sch, gpio_num, GLV);

	bit = sch_gpio_bit(sch, gpio_num);



	curr_vals = inb(sch->iobase + offset);



	if (val)

		outb(curr_vals | (1 << bit), sch->iobase + offset);

	else

		outb((curr_vals & ~(1 << bit)), sch->iobase + offset);



	spin_unlock(&sch->lock);

	spin_unlock(&sch->lock);

}

}
@@ -139,18 +123,9 @@ static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num, 
				  int val)

				  int val)

{

{

	struct sch_gpio *sch = to_sch_gpio(gc);

	struct sch_gpio *sch = to_sch_gpio(gc);

	u8 curr_dirs;

	unsigned short offset, bit;





	spin_lock(&sch->lock);

	spin_lock(&sch->lock);



	sch_gpio_reg_set(gc, gpio_num, GIO, 0);

	offset = sch_gpio_offset(sch, gpio_num, GIO);

	bit = sch_gpio_bit(sch, gpio_num);



	curr_dirs = inb(sch->iobase + offset);

	if (curr_dirs & (1 << bit))

		outb(curr_dirs & ~(1 << bit), sch->iobase + offset);



	spin_unlock(&sch->lock);

	spin_unlock(&sch->lock);





	/*

	/*
@@ -209,13 +184,13 @@ static int sch_gpio_probe(struct platform_device *pdev) 
		 * GPIO7 is configured by the CMC as SLPIOVR

		 * GPIO7 is configured by the CMC as SLPIOVR

		 * Enable GPIO[9:8] core powered gpios explicitly

		 * Enable GPIO[9:8] core powered gpios explicitly

		 */

		 */

		sch_gpio_enable(sch, 8);

		sch_gpio_reg_set(&sch->chip, 8, GEN, 1);

		sch_gpio_enable(sch, 9);

		sch_gpio_reg_set(&sch->chip, 9, GEN, 1);

		/*

		/*

		 * SUS_GPIO[2:0] enabled by default

		 * SUS_GPIO[2:0] enabled by default

		 * Enable SUS_GPIO3 resume powered gpio explicitly

		 * Enable SUS_GPIO3 resume powered gpio explicitly

		 */

		 */

		sch_gpio_enable(sch, 13);

		sch_gpio_reg_set(&sch->chip, 13, GEN, 1);

		break;

		break;





	case PCI_DEVICE_ID_INTEL_ITC_LPC:

	case PCI_DEVICE_ID_INTEL_ITC_LPC: