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Commit 920cda38 authored by Chad Reese's avatar Chad Reese Committed by Ralf Baechle
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MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. 



CN38XX pass 1 required icache prefetching to be turned off. This chip never
reached production and is long dead. Other processor specific icache settings
are done by the bootloader. Remove these bits from the kernel.

Signed-off-by: default avatarChad Reese <kreese@caviumnetworks.com>
Signed-off-by: default avatarAleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8944/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 726da2f8

arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h

+0 −20
Original line number Diff line number Diff line
@@ -37,26 +37,6 @@ 
	# Needed for octeon specific memcpy

	or  v0, v0, 0x5001

	xor v0, v0, 0x1001

	# Read the processor ID register

	mfc0 v1, CP0_PRID_REG

	# Disable instruction prefetching (Octeon Pass1 errata)

	or  v0, v0, 0x2000

	# Skip reenable of prefetching for Octeon Pass1

	beq v1, CP0_PRID_OCTEON_PASS1, skip

	nop

	# Reenable instruction prefetching, not on Pass1

	xor v0, v0, 0x2000

	# Strip off pass number off of processor id

	srl v1, 8

	sll v1, 8

	# CN30XX needs some extra stuff turned off for better performance

	bne v1, CP0_PRID_OCTEON_CN30XX, skip

	nop

	# CN30XX Use random Icache replacement

	or  v0, v0, 0x400

	# CN30XX Disable instruction prefetching

	or  v0, v0, 0x2000

skip:

	# First clear off CvmCtl[IPPCI] bit and move the performance

	# counters interrupt to IRQ 6

	dli	v1, ~(7 << 7)