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Commit 907b28c5 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
Browse files

drm/i915: Colocate all GT access routines in the same file 



Currently, the register access code is split between i915_drv.c and
intel_pm.c. It only bares a superficial resemblance to the reset of the
powermanagement code, so move it all into its own file. This is to ease
further patches to enforce serialised register access.

v2: Scan for random abuse of I915_WRITE_NOTRACE
v3: Take the opportunity to rename the GT functions as uncore. Uncore is
the term used by the hardware design (and bspec) for all functions
outside of the GPU (and CPU) cores in what is also known as the System
Agent.
v4: Rebase onto SNB rc6 fixes

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarBen Widawsky <ben@bwidawsk.net>
[danvet: Wrestle patch into applying and inline
intel_uncore_early_sanitize (plus move the old comment to the new
function). Also keep the _santize postfix for intel_uncore_sanitize.]
[danvet: Squash in fixup spotted by Chris on irc: We need to call
intel_pm_init before intel_uncore_sanitize since the later will call
cancel_work on the delayed rps setup work the former initializes.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent cb54b53a

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o \ 
	  intel_sprite.o \

	  intel_opregion.o \

	  intel_sideband.o \

	  intel_uncore.o \

	  dvo_ch7xxx.o \

	  dvo_ch7017.o \

	  dvo_ivch.o \

drivers/gpu/drm/i915/i915_debugfs.c

+6 −6
Original line number Diff line number Diff line
@@ -989,9 +989,9 @@ static int gen6_drpc_info(struct seq_file *m) 
	if (ret)

		return ret;



	spin_lock_irq(&dev_priv->gt_lock);

	forcewake_count = dev_priv->forcewake_count;

	spin_unlock_irq(&dev_priv->gt_lock);

	spin_lock_irq(&dev_priv->uncore.lock);

	forcewake_count = dev_priv->uncore.forcewake_count;

	spin_unlock_irq(&dev_priv->uncore.lock);



	if (forcewake_count) {

		seq_puts(m, "RC information inaccurate because somebody "
@@ -1375,9 +1375,9 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned forcewake_count;



	spin_lock_irq(&dev_priv->gt_lock);

	forcewake_count = dev_priv->forcewake_count;

	spin_unlock_irq(&dev_priv->gt_lock);

	spin_lock_irq(&dev_priv->uncore.lock);

	forcewake_count = dev_priv->uncore.forcewake_count;

	spin_unlock_irq(&dev_priv->uncore.lock);



	seq_printf(m, "forcewake count = %u\n", forcewake_count);

drivers/gpu/drm/i915/i915_dma.c

+5 −20
Original line number Diff line number Diff line
@@ -1435,22 +1435,6 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv) 
#undef SEP_COMMA

}



/**

 * intel_early_sanitize_regs - clean up BIOS state

 * @dev: DRM device

 *

 * This function must be called before we do any I915_READ or I915_WRITE. Its

 * purpose is to clean up any state left by the BIOS that may affect us when

 * reading and/or writing registers.

 */

static void intel_early_sanitize_regs(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (HAS_FPGA_DBG_UNCLAIMED(dev))

		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

}



/**

 * i915_driver_load - setup chip and create an initial config

 * @dev: DRM device
@@ -1493,7 +1477,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	spin_lock_init(&dev_priv->irq_lock);

	spin_lock_init(&dev_priv->gpu_error.lock);

	spin_lock_init(&dev_priv->backlight.lock);

	spin_lock_init(&dev_priv->gt_lock);

	spin_lock_init(&dev_priv->uncore.lock);

	mutex_init(&dev_priv->dpio_lock);

	mutex_init(&dev_priv->rps.hw_lock);

	mutex_init(&dev_priv->modeset_restore_lock);
@@ -1529,7 +1513,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
		goto put_bridge;

	}



	intel_early_sanitize_regs(dev);

	intel_uncore_early_sanitize(dev);



	if (IS_HASWELL(dev) && (I915_READ(HSW_EDRAM_PRESENT) == 1)) {

		/* The docs do not explain exactly how the calculation can be
@@ -1602,8 +1586,9 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	intel_detect_pch(dev);



	intel_irq_init(dev);

	intel_gt_sanitize(dev);

	intel_gt_init(dev);

	intel_pm_init(dev);

	intel_uncore_sanitize(dev);

	intel_uncore_init(dev);



	/* Try to make sure MCHBAR is enabled before poking at it */

	intel_setup_mchbar(dev);

drivers/gpu/drm/i915/i915_drv.c

+2 −269
Original line number Diff line number Diff line
@@ -723,7 +723,7 @@ static int i915_drm_thaw(struct drm_device *dev) 
{

	int error = 0;



	intel_gt_sanitize(dev);

	intel_uncore_sanitize(dev);



	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		mutex_lock(&dev->struct_mutex);
@@ -749,7 +749,7 @@ int i915_resume(struct drm_device *dev) 


	pci_set_master(dev->pdev);



	intel_gt_sanitize(dev);

	intel_uncore_sanitize(dev);



	/*

	 * Platforms with opregion should have sane BIOS, older ones (gen3 and
@@ -770,140 +770,6 @@ int i915_resume(struct drm_device *dev) 
	return 0;

}



static int i8xx_do_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (IS_I85X(dev))

		return -ENODEV;



	I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);

	POSTING_READ(D_STATE);



	if (IS_I830(dev) || IS_845G(dev)) {

		I915_WRITE(DEBUG_RESET_I830,

			   DEBUG_RESET_DISPLAY |

			   DEBUG_RESET_RENDER |

			   DEBUG_RESET_FULL);

		POSTING_READ(DEBUG_RESET_I830);

		msleep(1);



		I915_WRITE(DEBUG_RESET_I830, 0);

		POSTING_READ(DEBUG_RESET_I830);

	}



	msleep(1);



	I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);

	POSTING_READ(D_STATE);



	return 0;

}



static int i965_reset_complete(struct drm_device *dev)

{

	u8 gdrst;

	pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);

	return (gdrst & GRDOM_RESET_ENABLE) == 0;

}



static int i965_do_reset(struct drm_device *dev)

{

	int ret;



	/*

	 * Set the domains we want to reset (GRDOM/bits 2 and 3) as

	 * well as the reset bit (GR/bit 0).  Setting the GR bit

	 * triggers the reset; when done, the hardware will clear it.

	 */

	pci_write_config_byte(dev->pdev, I965_GDRST,

			      GRDOM_RENDER | GRDOM_RESET_ENABLE);

	ret =  wait_for(i965_reset_complete(dev), 500);

	if (ret)

		return ret;



	/* We can't reset render&media without also resetting display ... */

	pci_write_config_byte(dev->pdev, I965_GDRST,

			      GRDOM_MEDIA | GRDOM_RESET_ENABLE);



	ret =  wait_for(i965_reset_complete(dev), 500);

	if (ret)

		return ret;



	pci_write_config_byte(dev->pdev, I965_GDRST, 0);



	return 0;

}



static int ironlake_do_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 gdrst;

	int ret;



	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);

	gdrst &= ~GRDOM_MASK;

	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,

		   gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);

	ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);

	if (ret)

		return ret;



	/* We can't reset render&media without also resetting display ... */

	gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);

	gdrst &= ~GRDOM_MASK;

	I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,

		   gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);

	return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);

}



static int gen6_do_reset(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int	ret;

	unsigned long irqflags;



	/* Hold gt_lock across reset to prevent any register access

	 * with forcewake not set correctly

	 */

	spin_lock_irqsave(&dev_priv->gt_lock, irqflags);



	/* Reset the chip */



	/* GEN6_GDRST is not in the gt power well, no need to check

	 * for fifo space for the write or forcewake the chip for

	 * the read

	 */

	I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);



	/* Spin waiting for the device to ack the reset request */

	ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);



	/* If reset with a user forcewake, try to restore, otherwise turn it off */

	if (dev_priv->forcewake_count)

		dev_priv->gt.force_wake_get(dev_priv);

	else

		dev_priv->gt.force_wake_put(dev_priv);



	/* Restore fifo count */

	dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);



	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);

	return ret;

}



int intel_gpu_reset(struct drm_device *dev)

{

	switch (INTEL_INFO(dev)->gen) {

	case 7:

	case 6: return gen6_do_reset(dev);

	case 5: return ironlake_do_reset(dev);

	case 4: return i965_do_reset(dev);

	case 2: return i8xx_do_reset(dev);

	default: return -ENODEV;

	}

}



/**

 * i915_reset - reset chip after a hang

 * @dev: drm device to reset
@@ -1233,136 +1099,3 @@ module_exit(i915_exit); 
MODULE_AUTHOR(DRIVER_AUTHOR);

MODULE_DESCRIPTION(DRIVER_DESC);

MODULE_LICENSE("GPL and additional rights");
 


/* We give fast paths for the really cool registers */

#define NEEDS_FORCE_WAKE(dev_priv, reg) \

	((HAS_FORCE_WAKE((dev_priv)->dev)) && \

	 ((reg) < 0x40000) &&            \

	 ((reg) != FORCEWAKE))

static void

ilk_dummy_write(struct drm_i915_private *dev_priv)

{

	/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up

	 * the chip from rc6 before touching it for real. MI_MODE is masked,

	 * hence harmless to write 0 into. */

	I915_WRITE_NOTRACE(MI_MODE, 0);

}



static void

hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)

{

	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&

	    (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {

		DRM_ERROR("Unknown unclaimed register before writing to %x\n",

			  reg);

		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

	}

}



static void

hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)

{

	if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&

	    (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {

		DRM_ERROR("Unclaimed write to %x\n", reg);

		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);

	}

}



#define __i915_read(x, y) \

u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \

	unsigned long irqflags; \

	u##x val = 0; \

	spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

	if (IS_GEN5(dev_priv->dev)) \

		ilk_dummy_write(dev_priv); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->gt.force_wake_get(dev_priv); \

		val = read##y(dev_priv->regs + reg); \

		if (dev_priv->forcewake_count == 0) \

			dev_priv->gt.force_wake_put(dev_priv); \

	} else { \

		val = read##y(dev_priv->regs + reg); \

	} \

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

	trace_i915_reg_rw(false, reg, val, sizeof(val)); \

	return val; \

}



__i915_read(8, b)

__i915_read(16, w)

__i915_read(32, l)

__i915_read(64, q)

#undef __i915_read



#define __i915_write(x, y) \

void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \

	unsigned long irqflags; \

	u32 __fifo_ret = 0; \

	trace_i915_reg_rw(true, reg, val, sizeof(val)); \

	spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \

	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \

		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \

	} \

	if (IS_GEN5(dev_priv->dev)) \

		ilk_dummy_write(dev_priv); \

	hsw_unclaimed_reg_clear(dev_priv, reg); \

	write##y(val, dev_priv->regs + reg); \

	if (unlikely(__fifo_ret)) { \

		gen6_gt_check_fifodbg(dev_priv); \

	} \

	hsw_unclaimed_reg_check(dev_priv, reg); \

	spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \

}

__i915_write(8, b)

__i915_write(16, w)

__i915_write(32, l)

__i915_write(64, q)

#undef __i915_write



static const struct register_whitelist {

	uint64_t offset;

	uint32_t size;

	uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */

} whitelist[] = {

	{ RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },

};



int i915_reg_read_ioctl(struct drm_device *dev,

			void *data, struct drm_file *file)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct drm_i915_reg_read *reg = data;

	struct register_whitelist const *entry = whitelist;

	int i;



	for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {

		if (entry->offset == reg->offset &&

		    (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))

			break;

	}



	if (i == ARRAY_SIZE(whitelist))

		return -EINVAL;



	switch (entry->size) {

	case 8:

		reg->val = I915_READ64(reg->offset);

		break;

	case 4:

		reg->val = I915_READ(reg->offset);

		break;

	case 2:

		reg->val = I915_READ16(reg->offset);

		break;

	case 1:

		reg->val = I915_READ8(reg->offset);

		break;

	default:

		WARN_ON(1);

		return -EINVAL;

	}



	return 0;

}

drivers/gpu/drm/i915/i915_drv.h

+19 −12
Original line number Diff line number Diff line
@@ -391,11 +391,20 @@ struct drm_i915_display_funcs { 
	/* pll clock increase/decrease */

};



struct drm_i915_gt_funcs {

struct intel_uncore_funcs {

	void (*force_wake_get)(struct drm_i915_private *dev_priv);

	void (*force_wake_put)(struct drm_i915_private *dev_priv);

};



struct intel_uncore {

	spinlock_t lock; /** lock is also taken in irq contexts. */



	struct intel_uncore_funcs funcs;



	unsigned fifo_count;

	unsigned forcewake_count;

};



#define DEV_INFO_FOR_EACH_FLAG(func, sep) \

	func(is_mobile) sep \

	func(is_i85x) sep \
@@ -1045,14 +1054,7 @@ typedef struct drm_i915_private { 


	void __iomem *regs;



	struct drm_i915_gt_funcs gt;

	/** gt_fifo_count and the subsequent register write are synchronized

	 * with dev->struct_mutex. */

	unsigned gt_fifo_count;

	/** forcewake_count is protected by gt_lock */

	unsigned forcewake_count;

	/** gt_lock is also taken in irq contexts. */

	spinlock_t gt_lock;

	struct intel_uncore uncore;



	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
@@ -1670,8 +1672,14 @@ void i915_handle_error(struct drm_device *dev, bool wedged); 


extern void intel_irq_init(struct drm_device *dev);

extern void intel_hpd_init(struct drm_device *dev);

extern void intel_gt_init(struct drm_device *dev);

extern void intel_gt_sanitize(struct drm_device *dev);

extern void intel_pm_init(struct drm_device *dev);



extern void intel_uncore_sanitize(struct drm_device *dev);

extern void intel_uncore_early_sanitize(struct drm_device *dev);

extern void intel_uncore_init(struct drm_device *dev);

extern void intel_uncore_reset(struct drm_device *dev);

extern void intel_uncore_clear_errors(struct drm_device *dev);

extern void intel_uncore_check_errors(struct drm_device *dev);



void

i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
@@ -2107,7 +2115,6 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 
 */

void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);

void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);

int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);



int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);

int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);