scsi: ufs: dt-bindings: add document for hisi-ufs

* Hisilicon Universal Flash Storage (UFS) Host Controller

UFS nodes are defined to describe on-chip UFS hardware macro.

Each UFS Host Controller should have its own node.

Required properties:

- compatible        : compatible list, contains one of the following -

					"hisilicon,hi3660-ufs", "jedec,ufs-1.1" for hisi ufs

					host controller present on Hi36xx chipset.

- reg               : should contain UFS register address space & UFS SYS CTRL register address,

- interrupt-parent  : interrupt device

- interrupts        : interrupt number

- clocks	        : List of phandle and clock specifier pairs

- clock-names       : List of clock input name strings sorted in the same

					order as the clocks property. "ref_clk", "phy_clk" is optional

- freq-table-hz     : Array of <min max> operating frequencies stored in the same

                      order as the clocks property. If this property is not

                      defined or a value in the array is "0" then it is assumed

                      that the frequency is set by the parent clock or a

                      fixed rate clock source.

- resets            : describe reset node register

- reset-names       : reset node register, the "rst" corresponds to reset the whole UFS IP.

Example:

	ufs: ufs@ff3b0000 {

		compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";

		/* 0: HCI standard */

		/* 1: UFS SYS CTRL */

		reg = <0x0 0xff3b0000 0x0 0x1000>,

			<0x0 0xff3b1000 0x0 0x1000>;

		interrupt-parent = <&gic>;

		interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,

			<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;

		clock-names = "ref_clk", "phy_clk";

		freq-table-hz = <0 0>, <0 0>;

		/* offset: 0x84; bit: 12  */

		resets = <&crg_rst 0x84 12>;

		reset-names = "rst";

	};

-lanes-per-direction	: number of lanes available per direction - either 1 or 2.

			  Note that it is assume same number of lanes is used both

			  directions at once. If not specified, default is 2 lanes per direction.

- resets            : reset node register

- reset-names       : describe reset node register, the "rst" corresponds to reset the whole UFS IP.

Note: If above properties are not defined it can be assumed that the supply

regulators or clocks are always on.

		vccq-max-microamp = 200000;

		vccq2-max-microamp = 200000;

		clocks = <&core 0>, <&ref 0>, <&iface 0>;

		clock-names = "core_clk", "ref_clk", "iface_clk";

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>;

		clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;

		clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";

		freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;

		resets = <&reset 0 1>;

		reset-names = "rst";

		phys = <&ufsphy1>;

		phy-names = "ufsphy";

	};