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Commit 8ec49422 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc 

Pull sparc updates from David Miller:
 "Mostly more sparc64 THP bug fixes, and a refactoring of SMP bootup on
  sparc32 from Sam Ravnborg."

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc32: refactor smp boot
  sparc64: Fix huge PMD to PTE translation for sun4u in TLB miss handler.
  sparc64: Fix tsb_grow() in atomic context.
  sparc64: Handle hugepage TSB being NULL.
  sparc64: Fix gfp_flags setting in tsb_grow().
parents 79a69d34 f9fd3488

arch/sparc/include/asm/hugetlb.h

+0 −1
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, 


static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)

{

	hugetlb_setup(mm);

}



static inline int is_hugepage_only_range(struct mm_struct *mm,

arch/sparc/include/asm/page_64.h

+2 −2
Original line number Diff line number Diff line
@@ -27,8 +27,8 @@ 
#ifndef __ASSEMBLY__



#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)

struct mm_struct;

extern void hugetlb_setup(struct mm_struct *mm);

struct pt_regs;

extern void hugetlb_setup(struct pt_regs *regs);

#endif



#define WANT_PAGE_VIRTUAL

arch/sparc/include/asm/tsb.h

+19 −9
Original line number Diff line number Diff line
@@ -157,17 +157,26 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; 
	andn		REG2, 0x7, REG2; \

	add		REG1, REG2, REG1;



	/* This macro exists only to make the PMD translator below easier

	 * to read.  It hides the ELF section switch for the sun4v code

	 * patching.

	/* These macros exists only to make the PMD translator below

	 * easier to read.  It hides the ELF section switch for the

	 * sun4v code patching.

	 */

#define OR_PTE_BIT(REG, NAME)				\

#define OR_PTE_BIT_1INSN(REG, NAME)			\

661:	or		REG, _PAGE_##NAME##_4U, REG;	\

	.section	.sun4v_1insn_patch, "ax";	\

	.word		661b;				\

	or		REG, _PAGE_##NAME##_4V, REG;	\

	.previous;



#define OR_PTE_BIT_2INSN(REG, TMP, NAME)		\

661:	sethi		%hi(_PAGE_##NAME##_4U), TMP;	\

	or		REG, TMP, REG;			\

	.section	.sun4v_2insn_patch, "ax";	\

	.word		661b;				\

	mov		-1, TMP;			\

	or		REG, _PAGE_##NAME##_4V, REG;	\

	.previous;



	/* Load into REG the PTE value for VALID, CACHE, and SZHUGE.  */

#define BUILD_PTE_VALID_SZHUGE_CACHE(REG)				   \

661:	sethi		%uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG;		   \
@@ -214,12 +223,13 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end; 
	 andn		REG1, PMD_HUGE_PROTBITS, REG2;			      \

	sllx		REG2, PMD_PADDR_SHIFT, REG2;			      \

	/* REG2 now holds PFN << PAGE_SHIFT */				      \

	andcc		REG1, PMD_HUGE_EXEC, %g0;			      \

	bne,a,pt	%xcc, 1f;					      \

	 OR_PTE_BIT(REG2, EXEC);					      \

1:	andcc		REG1, PMD_HUGE_WRITE, %g0;			      \

	andcc		REG1, PMD_HUGE_WRITE, %g0;			      \

	bne,a,pt	%xcc, 1f;					      \

	 OR_PTE_BIT(REG2, W);						      \

	 OR_PTE_BIT_1INSN(REG2, W);					      \

1:	andcc		REG1, PMD_HUGE_EXEC, %g0;			      \

	be,pt		%xcc, 1f;					      \

	 nop;								      \

	OR_PTE_BIT_2INSN(REG2, REG1, EXEC);				      \

	/* REG1 can now be clobbered, build final PTE */		      \

1:	BUILD_PTE_VALID_SZHUGE_CACHE(REG1);				      \

	ba,pt		%xcc, PTE_LABEL;				      \

arch/sparc/kernel/kernel.h

+12 −0
Original line number Diff line number Diff line
@@ -48,6 +48,10 @@ extern void sun4m_init_IRQ(void); 
extern void sun4m_unmask_profile_irq(void);

extern void sun4m_clear_profile_irq(int cpu);



/* sun4m_smp.c */

void sun4m_cpu_pre_starting(void *arg);

void sun4m_cpu_pre_online(void *arg);



/* sun4d_irq.c */

extern spinlock_t sun4d_imsk_lock;
@@ -60,6 +64,14 @@ extern int show_sun4d_interrupts(struct seq_file *, void *); 
extern void sun4d_distribute_irqs(void);

extern void sun4d_free_irq(unsigned int irq, void *dev_id);



/* sun4d_smp.c */

void sun4d_cpu_pre_starting(void *arg);

void sun4d_cpu_pre_online(void *arg);



/* leon_smp.c */

void leon_cpu_pre_starting(void *arg);

void leon_cpu_pre_online(void *arg);



/* head_32.S */

extern unsigned int t_nmi[];

extern unsigned int linux_trap_ipi15_sun4d[];

arch/sparc/kernel/leon_smp.c

+9 −24
Original line number Diff line number Diff line
@@ -69,31 +69,19 @@ static inline unsigned long do_swap(volatile unsigned long *ptr, 
	return val;

}



void __cpuinit leon_callin(void)

void __cpuinit leon_cpu_pre_starting(void *arg)

{

	int cpuid = hard_smp_processor_id();



	local_ops->cache_all();

	local_ops->tlb_all();

	leon_configure_cache_smp();

}



	notify_cpu_starting(cpuid);



	/* Get our local ticker going. */

	register_percpu_ce(cpuid);



	calibrate_delay();

	smp_store_cpu_info(cpuid);



	local_ops->cache_all();

	local_ops->tlb_all();

void __cpuinit leon_cpu_pre_online(void *arg)

{

	int cpuid = hard_smp_processor_id();



	/*

	 * Unblock the master CPU _only_ when the scheduler state

	 * of all secondary CPUs will be up-to-date, so after

	 * the SMP initialization the master will be just allowed

	 * to call the scheduler code.

	 * Allow master to continue.

	/* Allow master to continue. The master will then give us the

	 * go-ahead by setting the smp_commenced_mask and will wait without

	 * timeouts until our setup is completed fully (signified by

	 * our bit being set in the cpu_online_mask).

	 */

	do_swap(&cpu_callin_map[cpuid], 1);
@@ -110,9 +98,6 @@ void __cpuinit leon_callin(void) 


	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))

		mb();



	local_irq_enable();

	set_cpu_online(cpuid, true);

}



/*