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Commit 8e52e279 authored by Grazvydas Ignotas's avatar Grazvydas Ignotas Committed by Samuel Ortiz
Browse files

mfd: Fix TWL4030 COR bit polarity for BCI SIH block 



The chip TRM documentation contradicts itself about this bit, page 174
of swcu050e says bit should be 0 for clear-on-read behavior, while
page 487 says it should be 1. Testing shows it should be 1, so set
the .set_cor flag accordingly. This is needed for upcoming BCI
charging driver to function.

Signed-off-by: default avatarGrazvydas Ignotas <notasas@gmail.com>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
parent a28dbea0

drivers/mfd/twl4030-irq.c

+2 −1
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ static const struct sih sih_modules_twl4030[6] = { 
		.name		= "bci",

		.module		= TWL4030_MODULE_INTERRUPTS,

		.control_offset	= TWL4030_INTERRUPTS_BCISIHCTRL,

		.set_cor	= true,

		.bits		= 12,

		.bytes_ixr	= 2,

		.edr_offset	= TWL4030_INTERRUPTS_BCIEDR1,
@@ -408,7 +409,7 @@ static int twl4030_init_sih_modules(unsigned line) 
		 * set Clear-On-Read (COR) bit.

		 *

		 * NOTE that sometimes COR polarity is documented as being

		 * inverted:  for MADC and BCI, COR=1 means "clear on write".

		 * inverted:  for MADC, COR=1 means "clear on write".

		 * And for PWR_INT it's not documented...

		 */

		if (sih->set_cor) {