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Commit 8deab114 authored by Mark Mason's avatar Mark Mason Committed by Ralf Baechle
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[MIPS] Updated Sibyte headers 



This is an update to the earlier patch for the sibyte headers, and superceeds
the previous patch.  Changes were necessary to get the tbprof driver working
on the bcm1480.

Patch to update Sibyte header files to match master versions maintained
at Broadcom.  This patch also corrects some whitespace problems, and
(hopefully) shouldn't introduce any new ones.

Signed-off-by: default avatarMark Mason <mason@broadcom.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent eacb9d61

include/asm-mips/sibyte/bcm1480_int.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -157,6 +157,7 @@ 
 * Mask values for each interrupt

 * Mask values for each interrupt

 */

 */





#define _BCM1480_INT_MASK(w,n)              _SB_MAKEMASK(w,((n) & 0x3F))

#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))

#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))

#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)

#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
@@ -195,6 +196,7 @@ 
#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)

#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)

#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)

#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)

#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)

#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)

#define M_BCM1480_INT_MBOX_ALL              _BCM1480_INT_MASK(8,K_BCM1480_INT_MBOX_0_0)

#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)

#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)

#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)

#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)

#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)

#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)

include/asm-mips/sibyte/bcm1480_mc.h

+27 −5
Original line number Original line Diff line number Diff line
@@ -382,6 +382,10 @@ 
#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)

#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)

#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)

#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)





#define M_BCM1480_MC_CS                  _SB_MAKEMASK(8,S_BCM1480_MC_CS0)

#define V_BCM1480_MC_CS(x)               _SB_MAKEVALUE(x,S_BCM1480_MC_CS0)

#define G_BCM1480_MC_CS(x)               _SB_GETVALUE(x,S_BCM1480_MC_CS0,M_BCM1480_MC_CS0)



#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)

#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)





/*

/*
@@ -412,6 +416,8 @@ 
#define K_BCM1480_MC_DRAM_TYPE_DDR2	    2

#define K_BCM1480_MC_DRAM_TYPE_DDR2	    2

#endif

#endif





#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0



#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)

#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)

#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)

#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
@@ -511,6 +517,22 @@ 
#define M_BCM1480_MC_WR_ODT6_CS6	    _SB_MAKEMASK1(31)

#define M_BCM1480_MC_WR_ODT6_CS6	    _SB_MAKEMASK1(31)





#define M_BCM1480_MC_CS_ODD_ODT_EN	    _SB_MAKEMASK1(32)

#define M_BCM1480_MC_CS_ODD_ODT_EN	    _SB_MAKEMASK1(32)



#define S_BCM1480_MC_ODT0	            0

#define M_BCM1480_MC_ODT0		    _SB_MAKEMASK(8,S_BCM1480_MC_ODT0)

#define V_BCM1480_MC_ODT0(x)		    _SB_MAKEVALUE(x,S_BCM1480_MC_ODT0)



#define S_BCM1480_MC_ODT2	            8

#define M_BCM1480_MC_ODT2		    _SB_MAKEMASK(8,S_BCM1480_MC_ODT2)

#define V_BCM1480_MC_ODT2(x)		    _SB_MAKEVALUE(x,S_BCM1480_MC_ODT2)



#define S_BCM1480_MC_ODT4	            16

#define M_BCM1480_MC_ODT4		    _SB_MAKEMASK(8,S_BCM1480_MC_ODT4)

#define V_BCM1480_MC_ODT4(x)		    _SB_MAKEVALUE(x,S_BCM1480_MC_ODT4)



#define S_BCM1480_MC_ODT6	            24

#define M_BCM1480_MC_ODT6		    _SB_MAKEMASK(8,S_BCM1480_MC_ODT6)

#define V_BCM1480_MC_ODT6(x)		    _SB_MAKEVALUE(x,S_BCM1480_MC_ODT6)

#endif

#endif





/*

/*

include/asm-mips/sibyte/bcm1480_regs.h

+20 −0
Original line number Original line Diff line number Diff line
@@ -230,6 +230,7 @@ 




#define A_BCM1480_DUART_IMRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))

#define A_BCM1480_DUART_IMRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_IMRREG(chan))

#define A_BCM1480_DUART_ISRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))

#define A_BCM1480_DUART_ISRREG(chan)	    (A_BCM1480_DUART(chan) + R_BCM1480_DUART_ISRREG(chan))

#define A_BCM1480_DUART_IN_PORT(chan)       (A_BCM1480_DUART(chan) + R_DUART_INP_ORT)





/*

/*

 * These constants are the absolute addresses.

 * These constants are the absolute addresses.
@@ -404,6 +405,21 @@ 
#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000		/* 0x0x0 */

#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000		/* 0x0x0 */

#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008		/* 0x0x8 */

#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008		/* 0x0x8 */





/*

 * these macros work together to build the address of a mailbox

 * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)

 * for mbox_0_set_cpu2 returns 0x00100240C8

 */

#define R_BCM1480_IMR_MAILBOX_CPU         0x00

#define R_BCM1480_IMR_MAILBOX_SET         0x08

#define R_BCM1480_IMR_MAILBOX_CLR         0x10

#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20

#define A_BCM1480_MAILBOX_REGISTER(num,reg,cpu) \

    (A_BCM1480_IMR_CPU0_BASE + \

     (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \

     (cpu * BCM1480_IMR_REGISTER_SPACING) + \

     (R_BCM1480_IMR_MAILBOX_0_CPU + reg))



/*  *********************************************************************

/*  *********************************************************************

    * System Performance Counter Registers (Section 4.7)

    * System Performance Counter Registers (Section 4.7)

    ********************************************************************* */

    ********************************************************************* */
@@ -428,6 +444,10 @@ 
#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500

#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500

#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508

#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508





#define BCM1480_SCD_NUM_PERF_CNT 8

#define BCM1480_SCD_PERF_CNT_SPACING 8

#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))



/*  *********************************************************************

/*  *********************************************************************

    * System Bus Watcher Registers (Section 4.8)

    * System Bus Watcher Registers (Section 4.8)

    ********************************************************************* */

    ********************************************************************* */

include/asm-mips/sibyte/bcm1480_scd.h

+32 −62
Original line number Original line Diff line number Diff line
@@ -10,7 +10,7 @@ 
    *

    *

    *********************************************************************

    *********************************************************************

    *

    *

    *  Copyright 2000,2001,2002,2003

    *  Copyright 2000,2001,2002,2003,2004,2005

    *  Broadcom Corporation. All rights reserved.

    *  Broadcom Corporation. All rights reserved.

    *

    *

    *  This program is free software; you can redistribute it and/or

    *  This program is free software; you can redistribute it and/or
@@ -78,6 +78,7 @@ 
#define K_SYS_PART_BCM1280          0x1206

#define K_SYS_PART_BCM1280          0x1206

#define K_SYS_PART_BCM1455          0x1407

#define K_SYS_PART_BCM1455          0x1407

#define K_SYS_PART_BCM1255          0x1257

#define K_SYS_PART_BCM1255          0x1257

#define K_SYS_PART_BCM1158          0x1156





/*

/*

 * Manufacturing Information Register (Table 14)

 * Manufacturing Information Register (Table 14)
@@ -237,58 +238,42 @@ 
 * System Performance Counter Configuration Register (Table 31)

 * System Performance Counter Configuration Register (Table 31)

 * Register: PERF_CNT_CFG_0

 * Register: PERF_CNT_CFG_0

 *

 *

 * Since the clear/enable bits are moved compared to the

 * SPC_CFG_SRC[0-3] is the same as the 1250.

 * 1250 and there are more fields, this register will be BCM1480 specific.

 * SPC_CFG_SRC[4-7] only exist on the 1480

 * The clear/enable bits are in different locations on the 1250 and 1480.

 */

 */





#define S_BCM1480_SPC_CFG_SRC0              0

#define S_SPC_CFG_SRC4              32

#define M_BCM1480_SPC_CFG_SRC0              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0)

#define M_SPC_CFG_SRC4              _SB_MAKEMASK(8,S_SPC_CFG_SRC4)

#define V_BCM1480_SPC_CFG_SRC0(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0)

#define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x,S_SPC_CFG_SRC4)

#define G_BCM1480_SPC_CFG_SRC0(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0)

#define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4)





#define S_BCM1480_SPC_CFG_SRC1              8

#define S_SPC_CFG_SRC5              40

#define M_BCM1480_SPC_CFG_SRC1              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1)

#define M_SPC_CFG_SRC5              _SB_MAKEMASK(8,S_SPC_CFG_SRC5)

#define V_BCM1480_SPC_CFG_SRC1(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1)

#define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x,S_SPC_CFG_SRC5)

#define G_BCM1480_SPC_CFG_SRC1(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1)

#define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5)





#define S_BCM1480_SPC_CFG_SRC2              16

#define S_SPC_CFG_SRC6              48

#define M_BCM1480_SPC_CFG_SRC2              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2)

#define M_SPC_CFG_SRC6              _SB_MAKEMASK(8,S_SPC_CFG_SRC6)

#define V_BCM1480_SPC_CFG_SRC2(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2)

#define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x,S_SPC_CFG_SRC6)

#define G_BCM1480_SPC_CFG_SRC2(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2)

#define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6)





#define S_BCM1480_SPC_CFG_SRC3              24

#define S_SPC_CFG_SRC7              56

#define M_BCM1480_SPC_CFG_SRC3              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3)

#define M_SPC_CFG_SRC7              _SB_MAKEMASK(8,S_SPC_CFG_SRC7)

#define V_BCM1480_SPC_CFG_SRC3(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3)

#define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x,S_SPC_CFG_SRC7)

#define G_BCM1480_SPC_CFG_SRC3(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3)

#define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7)



#define S_BCM1480_SPC_CFG_SRC4              32

#define M_BCM1480_SPC_CFG_SRC4              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4)

#define V_BCM1480_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4)

#define G_BCM1480_SPC_CFG_SRC4(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4)



#define S_BCM1480_SPC_CFG_SRC5              40

#define M_BCM1480_SPC_CFG_SRC5              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5)

#define V_BCM1480_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5)

#define G_BCM1480_SPC_CFG_SRC5(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5)



#define S_BCM1480_SPC_CFG_SRC6              48

#define M_BCM1480_SPC_CFG_SRC6              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6)

#define V_BCM1480_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6)

#define G_BCM1480_SPC_CFG_SRC6(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6)



#define S_BCM1480_SPC_CFG_SRC7              56

#define M_BCM1480_SPC_CFG_SRC7              _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7)

#define V_BCM1480_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7)

#define G_BCM1480_SPC_CFG_SRC7(x)           _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7)





/*

/*

 * System Performance Counter Control Register (Table 32)

 * System Performance Counter Control Register (Table 32)

 * Register: PERF_CNT_CFG_1

 * Register: PERF_CNT_CFG_1

 * BCM1480 specific

 * BCM1480 specific

 */

 */



#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)

#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)

#define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)

#define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)

#if SIBYTE_HDR_FEATURE_CHIP(1480)

#define M_SPC_CFG_CLEAR			M_BCM1480_SPC_CFG_CLEAR

#define M_SPC_CFG_ENABLE		M_BCM1480_SPC_CFG_ENABLE

#endif





/*

/*

 * System Performance Counters (Table 33)

 * System Performance Counters (Table 33)
@@ -405,20 +390,10 @@ 
 * Trace Control Register (Table 49)

 * Trace Control Register (Table 49)

 * Register: TRACE_CFG

 * Register: TRACE_CFG

 *

 *

 * Bits 0..8 are the same as the BCM1250, rest are different.

 * BCM1480 changes to this register (other than location of the CUR_ADDR field)

 * Entire register is redefined below.

 * are defined below.

 */

 */





#define M_BCM1480_SCD_TRACE_CFG_RESET       _SB_MAKEMASK1(0)

#define M_BCM1480_SCD_TRACE_CFG_START_READ  _SB_MAKEMASK1(1)

#define M_BCM1480_SCD_TRACE_CFG_START       _SB_MAKEMASK1(2)

#define M_BCM1480_SCD_TRACE_CFG_STOP        _SB_MAKEMASK1(3)

#define M_BCM1480_SCD_TRACE_CFG_FREEZE      _SB_MAKEMASK1(4)

#define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)

#define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL  _SB_MAKEMASK1(6)

#define M_BCM1480_SCD_TRACE_CFG_FULL        _SB_MAKEMASK1(7)

#define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT   _SB_MAKEMASK1(8)



#define S_BCM1480_SCD_TRACE_CFG_MODE        16

#define S_BCM1480_SCD_TRACE_CFG_MODE        16

#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)

#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE)

#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)

#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE)
@@ -428,9 +403,4 @@ 
#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT	1

#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT	1

#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID	2

#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID	2





#define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR    24

#define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR    _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)

#define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR)

#define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR)



#endif /* _BCM1480_SCD_H */
 
#endif /* _BCM1480_SCD_H */

include/asm-mips/sibyte/board.h

+12 −2
Original line number Original line Diff line number Diff line 
/*

/*

 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation

 * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation

 *

 *

 * This program is free software; you can redistribute it and/or

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License

 * modify it under the terms of the GNU General Public License
@@ -19,8 +19,8 @@ 
#ifndef _SIBYTE_BOARD_H

#ifndef _SIBYTE_BOARD_H

#define _SIBYTE_BOARD_H

#define _SIBYTE_BOARD_H







#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \

#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \

    defined(CONFIG_SIBYTE_PT1120) || defined(CONFIG_SIBYTE_PT1125) || \

    defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \

    defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \

    defined(CONFIG_SIBYTE_LITTLESUR)

    defined(CONFIG_SIBYTE_LITTLESUR)

#include <asm/sibyte/swarm.h>

#include <asm/sibyte/swarm.h>
@@ -55,6 +55,16 @@ 
#define setleds(t0,t1,c0,c1,c2,c3)

#define setleds(t0,t1,c0,c1,c2,c3)

#endif /* LEDS_PHYS */

#endif /* LEDS_PHYS */





#else



void swarm_setup(void);



#ifdef LEDS_PHYS

extern void setleds(char *str);

#else

#define setleds(s) do { } while (0)

#endif /* LEDS_PHYS */



#endif /* __ASSEMBLY__ */

#endif /* __ASSEMBLY__ */





#endif /* _SIBYTE_BOARD_H */
 
#endif /* _SIBYTE_BOARD_H */