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Commit 8d98aa39 authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
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r8169: replace magic numbers with PCI MRRS constant 



Replace magic number "0x5 << MAX_READ_REQUEST_SHIFT" with the
appropriate constant as defined in PCI core.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a5724fc3

drivers/net/ethernet/realtek/r8169.c

+19 −20
Original line number Diff line number Diff line
@@ -84,7 +84,6 @@ 
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */

static const int multicast_filter_limit = 32;



#define MAX_READ_REQUEST_SHIFT	12

#define TX_DMA_BURST	7	/* Maximum PCI burst, '7' is unlimited */

#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
@@ -5125,7 +5124,7 @@ static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 
{

	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);

	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);

	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

}



static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5151,7 +5150,7 @@ static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 
	RTL_W8(tp, MaxTxPacketSize, 0x0c);

	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);

	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);

	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);

}



static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5163,7 +5162,7 @@ static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) 
static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)

{

	rtl_tx_performance_tweak(tp,

		(0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);

		PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);

}



static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
@@ -5736,7 +5735,7 @@ static void rtl_hw_start_8168bb(struct rtl8169_private *tp) 
	RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);



	if (tp->dev->mtu <= ETH_DATA_LEN) {

		rtl_tx_performance_tweak(tp, (0x5 << MAX_READ_REQUEST_SHIFT) |

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |

					 PCI_EXP_DEVCTL_NOSNOOP_EN);

	}

}
@@ -5757,7 +5756,7 @@ static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_disable_clock_request(tp);
@@ -5788,7 +5787,7 @@ static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 
	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

}
@@ -5805,7 +5804,7 @@ static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 
	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

}
@@ -5862,7 +5861,7 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp) 
	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W16(tp, CPlusCmd, RTL_R16(tp, CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);

}
@@ -5872,7 +5871,7 @@ static void rtl_hw_start_8168dp(struct rtl8169_private *tp) 
	rtl_csi_access_enable_1(tp);



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
@@ -5889,7 +5888,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 


	rtl_csi_access_enable_1(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
@@ -5921,7 +5920,7 @@ static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 
	rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
@@ -5946,7 +5945,7 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 
	rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));



	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
@@ -5976,7 +5975,7 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) 
{

	rtl_csi_access_enable_2(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
@@ -6047,7 +6046,7 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp) 


	rtl_csi_access_enable_1(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6147,7 +6146,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 


	rtl_csi_access_enable_1(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6229,7 +6228,7 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 


	rtl_csi_access_enable_1(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
@@ -6495,7 +6494,7 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 


	RTL_W8(tp, DBG_REG, FIX_NAK_1);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W8(tp, Config1,

	       LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
@@ -6512,7 +6511,7 @@ static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 
{

	rtl_csi_access_enable_2(tp);



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);

	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
@@ -6575,7 +6574,7 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp) 


	rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));



	rtl_tx_performance_tweak(tp, 0x5 << MAX_READ_REQUEST_SHIFT);

	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);