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Commit 8d3c6294 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2018-02-14-1' of... 

Merge tag 'drm-intel-fixes-2018-02-14-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes

There are important fixes for VLV with MIPI/DSI panels,
2 clean-up patches needed for this MIPI/DSI fix,
and many fixes for GEM including fixes for Perf OA and PMU,
and fixes on scheduler and preemption.

This also includes GVT fixes: "This has one to fix GTT mmio 8b
access from guest and two simple ones for mmio switch and typo fix"

* tag 'drm-intel-fixes-2018-02-14-1' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915: Fix DSI panels with v1 MIPI sequences without a DEASSERT sequence v3
  drm/i915: Free memdup-ed DSI VBT data structures on driver_unload
  drm/i915: Add intel_bios_cleanup() function
  drm/i915/vlv: Add cdclk workaround for DSI
  drm/i915/gvt: fix one typo of render_mmio trace
  drm/i915/gvt: Support BAR0 8-byte reads/writes
  drm/i915/gvt: add 0xe4f0 into gen9 render list
  drm/i915/pmu: Fix building without CONFIG_PM
  drm/i915/pmu: Fix sleep under atomic in RC6 readout
  drm/i915/pmu: Fix PMU enable vs execlists tasklet race
  drm/i915: Lock out execlist tasklet while peeking inside for busy-stats
  drm/i915/breadcrumbs: Ignore unsubmitted signalers
  drm/i915: Don't wake the device up to check if the engine is asleep
  drm/i915: Avoid truncation before clamping userspace's priority value
  drm/i915/perf: Fix compiler warning for string truncation
  drm/i915/perf: Fix compiler warning for string truncation
parents 6bdd5b4e ee622fe7

drivers/gpu/drm/i915/gvt/kvmgt.c

+49 −2
Original line number Diff line number Diff line
@@ -733,6 +733,25 @@ static ssize_t intel_vgpu_rw(struct mdev_device *mdev, char *buf, 
	return ret == 0 ? count : ret;

}



static bool gtt_entry(struct mdev_device *mdev, loff_t *ppos)

{

	struct intel_vgpu *vgpu = mdev_get_drvdata(mdev);

	unsigned int index = VFIO_PCI_OFFSET_TO_INDEX(*ppos);

	struct intel_gvt *gvt = vgpu->gvt;

	int offset;



	/* Only allow MMIO GGTT entry access */

	if (index != PCI_BASE_ADDRESS_0)

		return false;



	offset = (u64)(*ppos & VFIO_PCI_OFFSET_MASK) -

		intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);



	return (offset >= gvt->device_info.gtt_start_offset &&

		offset < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt)) ?

			true : false;

}



static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf,

			size_t count, loff_t *ppos)

{
@@ -742,7 +761,21 @@ static ssize_t intel_vgpu_read(struct mdev_device *mdev, char __user *buf, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes read */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, false);

			if (ret <= 0)

				goto read_err;



			if (copy_to_user(buf, &val, sizeof(val)))

				goto read_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
@@ -802,7 +835,21 @@ static ssize_t intel_vgpu_write(struct mdev_device *mdev, 
	while (count) {

		size_t filled;



		if (count >= 4 && !(*ppos % 4)) {

		/* Only support GGTT entry 8 bytes write */

		if (count >= 8 && !(*ppos % 8) &&

			gtt_entry(mdev, ppos)) {

			u64 val;



			if (copy_from_user(&val, buf, sizeof(val)))

				goto write_err;



			ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),

					ppos, true);

			if (ret <= 0)

				goto write_err;



			filled = 8;

		} else if (count >= 4 && !(*ppos % 4)) {

			u32 val;



			if (copy_from_user(&val, buf, sizeof(val)))

drivers/gpu/drm/i915/gvt/mmio_context.c

+1 −0
Original line number Diff line number Diff line
@@ -118,6 +118,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { 
	{RCS, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */

	{RCS, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */

	{RCS, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */

	{RCS, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */

	{RCS, TRVATTL3PTRDW(0), 0, false}, /* 0x4de0 */

	{RCS, TRVATTL3PTRDW(1), 0, false}, /* 0x4de4 */

	{RCS, TRNULLDETCT, 0, false}, /* 0x4de8 */

drivers/gpu/drm/i915/gvt/trace.h

+1 −1
Original line number Diff line number Diff line
@@ -333,7 +333,7 @@ TRACE_EVENT(render_mmio, 
	TP_PROTO(int old_id, int new_id, char *action, unsigned int reg,

		 unsigned int old_val, unsigned int new_val),



	TP_ARGS(old_id, new_id, action, reg, new_val, old_val),

	TP_ARGS(old_id, new_id, action, reg, old_val, new_val),



	TP_STRUCT__entry(

		__field(int, old_id)

drivers/gpu/drm/i915/i915_drv.c

+1 −13
Original line number Diff line number Diff line
@@ -1433,19 +1433,7 @@ void i915_driver_unload(struct drm_device *dev) 


	intel_modeset_cleanup(dev);



	/*

	 * free the memory space allocated for the child device

	 * config parsed from VBT

	 */

	if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {

		kfree(dev_priv->vbt.child_dev);

		dev_priv->vbt.child_dev = NULL;

		dev_priv->vbt.child_dev_num = 0;

	}

	kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);

	dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;

	kfree(dev_priv->vbt.lfp_lvds_vbt_mode);

	dev_priv->vbt.lfp_lvds_vbt_mode = NULL;

	intel_bios_cleanup(dev_priv);



	vga_switcheroo_unregister_client(pdev);

	vga_client_register(pdev, NULL, NULL, NULL);

drivers/gpu/drm/i915/i915_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -1349,6 +1349,7 @@ struct intel_vbt_data { 
		u32 size;

		u8 *data;

		const u8 *sequence[MIPI_SEQ_MAX];

		u8 *deassert_seq; /* Used by fixup_mipi_sequences() */

	} dsi;



	int crt_ddc_pin;
@@ -3657,6 +3658,7 @@ extern void intel_i2c_reset(struct drm_i915_private *dev_priv); 


/* intel_bios.c */

void intel_bios_init(struct drm_i915_private *dev_priv);

void intel_bios_cleanup(struct drm_i915_private *dev_priv);

bool intel_bios_is_valid_vbt(const void *buf, size_t size);

bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);

bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);