Merge branch 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux into drm-next

	atombios_encoders.o amdgpu_sa.o atombios_i2c.o \

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o

# add asic specific block

amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o

amdgpu-y += \

	vi.o mxgpu_vi.o

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o

# add GMC block

amdgpu-y += \

	gmc_v7_0.o \

	gmc_v8_0.o

	gmc_v8_0.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o

# add IH block

amdgpu-y += \

	amdgpu_ih.o \

	iceland_ih.o \

	tonga_ih.o \

	cz_ih.o

	cz_ih.o \

	vega10_ih.o

# add PSP block

amdgpu-y += \

	amdgpu_psp.o \

	psp_v3_1.o

# add SMC block

amdgpu-y += \

# add GFX block

amdgpu-y += \

	amdgpu_gfx.o \

	gfx_v8_0.o

	gfx_v8_0.o \

	gfx_v9_0.o

# add async DMA block

amdgpu-y += \

	sdma_v2_4.o \

	sdma_v3_0.o

	sdma_v3_0.o \

	sdma_v4_0.o

# add UVD block

amdgpu-y += \

	amdgpu_uvd.o \

	uvd_v5_0.o \

	uvd_v6_0.o

	uvd_v6_0.o \

	uvd_v7_0.o

# add VCE block

amdgpu-y += \

	amdgpu_vce.o \

	vce_v3_0.o

	vce_v3_0.o \

	vce_v4_0.o

# add amdkfd interfaces

amdgpu-y += \

#include "amdgpu_irq.h"

#include "amdgpu_ucode.h"

#include "amdgpu_ttm.h"

#include "amdgpu_psp.h"

#include "amdgpu_gds.h"

#include "amdgpu_sync.h"

#include "amdgpu_ring.h"

#include "amd_powerplay.h"

#include "amdgpu_dpm.h"

#include "amdgpu_acp.h"

#include "amdgpu_uvd.h"

#include "amdgpu_vce.h"

#include "gpu_scheduler.h"

#include "amdgpu_virt.h"

extern int amdgpu_msi;

extern int amdgpu_lockup_timeout;

extern int amdgpu_dpm;

extern int amdgpu_smc_load_fw;

extern int amdgpu_fw_load_type;

extern int amdgpu_aspm;

extern int amdgpu_runtime_pm;

extern unsigned amdgpu_ip_block_mask;

extern char *amdgpu_virtual_display;

extern unsigned amdgpu_pp_feature_mask;

extern int amdgpu_vram_page_split;

extern int amdgpu_ngg;

extern int amdgpu_prim_buf_per_se;

extern int amdgpu_pos_buf_per_se;

extern int amdgpu_cntl_sb_buf_per_se;

extern int amdgpu_param_buf_per_se;

#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS	        3000

#define AMDGPU_MAX_USEC_TIMEOUT			100000	/* 100 ms */

#define AMDGPU_IB_POOL_SIZE			16

#define AMDGPU_DEBUGFS_MAX_COMPONENTS		32

#define AMDGPUFB_CONN_LIMIT			4

#define AMDGPU_BIOS_NUM_SCRATCH			8

#define AMDGPU_BIOS_NUM_SCRATCH			16

/* max number of IP instances */

#define AMDGPU_MAX_SDMA_INSTANCES		2

/* max number of VMHUB */

#define AMDGPU_MAX_VMHUBS			2

#define AMDGPU_MMHUB				0

#define AMDGPU_GFXHUB				1

/* hardcode that limit for now */

#define AMDGPU_VA_RESERVED_SIZE			(8 << 20)

	void (*set_pte_pde)(struct amdgpu_ib *ib,

			    uint64_t pe,

			    uint64_t addr, unsigned count,

			    uint32_t incr, uint32_t flags);

			    uint32_t incr, uint64_t flags);

};

/* provided by the gmc block */

			   void *cpu_pt_addr, /* cpu addr of page table */

			   uint32_t gpu_page_idx, /* pte/pde to update */

			   uint64_t addr, /* addr to write into pte/pde */

			   uint32_t flags); /* access flags */

			   uint64_t flags); /* access flags */

	/* enable/disable PRT support */

	void (*set_prt)(struct amdgpu_device *adev, bool enable);

	/* set pte flags based per asic */

	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,

				     uint32_t flags);

};

/* provided by the mc block */

struct amdgpu_mc_funcs {

	/* adjust mc addr in fb for APU case */

	u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr);

};

/* provided by the ih block */

	struct page			**pages;

#endif

	bool				ready;

	/* Asic default pte flags */

	uint64_t			gart_pte_flags;

	const struct amdgpu_gart_funcs *gart_funcs;

};

			int pages);

int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,

		     int pages, struct page **pagelist,

		     dma_addr_t *dma_addr, uint32_t flags);

		     dma_addr_t *dma_addr, uint64_t flags);

int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);

/*

 * VMHUB structures, functions & helpers

 */

struct amdgpu_vmhub {

	uint32_t	ctx0_ptb_addr_lo32;

	uint32_t	ctx0_ptb_addr_hi32;

	uint32_t	vm_inv_eng0_req;

	uint32_t	vm_inv_eng0_ack;

	uint32_t	vm_context0_cntl;

	uint32_t	vm_l2_pro_fault_status;

	uint32_t	vm_l2_pro_fault_cntl;

	uint32_t	(*get_invalidate_req)(unsigned int vm_id);

	uint32_t	(*get_vm_protection_bits)(void);

};

/*

 * GPU MC structures, functions & helpers

 */

	uint32_t		vram_type;

	uint32_t                srbm_soft_reset;

	struct amdgpu_mode_mc_save save;

	bool			prt_warning;

	/* apertures */

	u64					shared_aperture_start;

	u64					shared_aperture_end;

	u64					private_aperture_start;

	u64					private_aperture_end;

	/* protects concurrent invalidation */

	spinlock_t		invalidate_lock;

	const struct amdgpu_mc_funcs *mc_funcs;

};

/*

	u32			num_doorbells;	/* Number of doorbells actually reserved for amdgpu. */

};

/*

 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space

 */

typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT

{

	/*

	 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in

	 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.

	 *  Compute related doorbells are allocated from 0x00 to 0x8a

	 */

	/* kernel scheduling */

	AMDGPU_DOORBELL64_KIQ                     = 0x00,

	/* HSA interface queue and debug queue */

	AMDGPU_DOORBELL64_HIQ                     = 0x01,

	AMDGPU_DOORBELL64_DIQ                     = 0x02,

	/* Compute engines */

	AMDGPU_DOORBELL64_MEC_RING0               = 0x03,

	AMDGPU_DOORBELL64_MEC_RING1               = 0x04,

	AMDGPU_DOORBELL64_MEC_RING2               = 0x05,

	AMDGPU_DOORBELL64_MEC_RING3               = 0x06,

	AMDGPU_DOORBELL64_MEC_RING4               = 0x07,

	AMDGPU_DOORBELL64_MEC_RING5               = 0x08,

	AMDGPU_DOORBELL64_MEC_RING6               = 0x09,

	AMDGPU_DOORBELL64_MEC_RING7               = 0x0a,

	/* User queue doorbell range (128 doorbells) */

	AMDGPU_DOORBELL64_USERQUEUE_START         = 0x0b,

	AMDGPU_DOORBELL64_USERQUEUE_END           = 0x8a,

	/* Graphics engine */

	AMDGPU_DOORBELL64_GFX_RING0               = 0x8b,

	/*

	 * Other graphics doorbells can be allocated here: from 0x8c to 0xef

	 * Graphics voltage island aperture 1

	 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive

	 */

	/* sDMA engines */

	AMDGPU_DOORBELL64_sDMA_ENGINE0            = 0xF0,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0     = 0xF1,

	AMDGPU_DOORBELL64_sDMA_ENGINE1            = 0xF2,

	AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1     = 0xF3,

	/* Interrupt handler */

	AMDGPU_DOORBELL64_IH                      = 0xF4,  /* For legacy interrupt ring buffer */

	AMDGPU_DOORBELL64_IH_RING1                = 0xF5,  /* For page migration request log */

	AMDGPU_DOORBELL64_IH_RING2                = 0xF6,  /* For page migration translation/invalidation log */

	/* VCN engine use 32 bits doorbell  */

	AMDGPU_DOORBELL64_VCN0_1                  = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */

	AMDGPU_DOORBELL64_VCN2_3                  = 0xF9,

	AMDGPU_DOORBELL64_VCN4_5                  = 0xFA,

	AMDGPU_DOORBELL64_VCN6_7                  = 0xFB,

	/* overlap the doorbell assignment with VCN as they are  mutually exclusive

	 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD

	 */

	AMDGPU_DOORBELL64_RING0_1                 = 0xF8,

	AMDGPU_DOORBELL64_RING2_3                 = 0xF9,

	AMDGPU_DOORBELL64_RING4_5                 = 0xFA,

	AMDGPU_DOORBELL64_RING6_7                 = 0xFB,

	AMDGPU_DOORBELL64_UVD_RING0_1             = 0xFC,

	AMDGPU_DOORBELL64_UVD_RING2_3             = 0xFD,

	AMDGPU_DOORBELL64_UVD_RING4_5             = 0xFE,

	AMDGPU_DOORBELL64_UVD_RING6_7             = 0xFF,

	AMDGPU_DOORBELL64_MAX_ASSIGNMENT          = 0xFF,

	AMDGPU_DOORBELL64_INVALID                 = 0xFFFF

} AMDGPU_DOORBELL64_ASSIGNMENT;

void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,

				phys_addr_t *aperture_base,

				size_t *aperture_size,

struct amdgpu_fpriv {

	struct amdgpu_vm	vm;

	struct amdgpu_bo_va	*prt_va;

	struct mutex		bo_list_lock;

	struct idr		bo_list_handles;

	struct amdgpu_ctx_mgr	ctx_mgr;

struct amdgpu_mec {

	struct amdgpu_bo	*hpd_eop_obj;

	u64			hpd_eop_gpu_addr;

	struct amdgpu_bo	*mec_fw_obj;

	u64			mec_fw_gpu_addr;

	u32 num_pipe;

	u32 num_mec;

	u32 num_queue;

	void			*mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];

};

struct amdgpu_kiq {

	uint32_t raster_config_1;

};

struct amdgpu_gca_config {

struct gb_addr_config {

	uint16_t pipe_interleave_size;

	uint8_t num_pipes;

	uint8_t max_compress_frags;

	uint8_t num_banks;

	uint8_t num_se;

	uint8_t num_rb_per_se;

};

struct amdgpu_gfx_config {

	unsigned max_shader_engines;

	unsigned max_tile_pipes;

	unsigned max_cu_per_sh;

	uint32_t tile_mode_array[32];

	uint32_t macrotile_mode_array[16];

	struct gb_addr_config gb_addr_config_fields;

	struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];

	/* gfx configure feature */

	uint32_t double_offchip_lds_buf;

};

struct amdgpu_cu_info {

	void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);

};

struct amdgpu_ngg_buf {

	struct amdgpu_bo	*bo;

	uint64_t		gpu_addr;

	uint32_t		size;

	uint32_t		bo_size;

};

enum {

	PRIM = 0,

	POS,

	CNTL,

	PARAM,

	NGG_BUF_MAX

};

struct amdgpu_ngg {

	struct amdgpu_ngg_buf	buf[NGG_BUF_MAX];

	uint32_t		gds_reserve_addr;

	uint32_t		gds_reserve_size;

	bool			init;

};

struct amdgpu_gfx {

	struct mutex			gpu_clock_mutex;

	struct amdgpu_gca_config	config;

	struct amdgpu_gfx_config	config;

	struct amdgpu_rlc		rlc;

	struct amdgpu_mec		mec;

	struct amdgpu_kiq		kiq;

	/* reset mask */

	uint32_t                        grbm_soft_reset;

	uint32_t                        srbm_soft_reset;

	bool                            in_reset;

	/* NGG */

	struct amdgpu_ngg		ngg;

};

int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);

void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);

int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);

void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);

void amdgpu_get_pcie_info(struct amdgpu_device *adev);

/*

 * UVD

 */

#define AMDGPU_DEFAULT_UVD_HANDLES	10

#define AMDGPU_MAX_UVD_HANDLES		40

#define AMDGPU_UVD_STACK_SIZE		(200*1024)

#define AMDGPU_UVD_HEAP_SIZE		(256*1024)

#define AMDGPU_UVD_SESSION_SIZE		(50*1024)

#define AMDGPU_UVD_FIRMWARE_OFFSET	256

struct amdgpu_uvd {

	struct amdgpu_bo	*vcpu_bo;

	void			*cpu_addr;

	uint64_t		gpu_addr;

	unsigned		fw_version;

	void			*saved_bo;

	unsigned		max_handles;

	atomic_t		handles[AMDGPU_MAX_UVD_HANDLES];

	struct drm_file		*filp[AMDGPU_MAX_UVD_HANDLES];

	struct delayed_work	idle_work;

	const struct firmware	*fw;	/* UVD firmware */

	struct amdgpu_ring	ring;

	struct amdgpu_irq_src	irq;

	bool			address_64_bit;

	bool			use_ctx_buf;

	struct amd_sched_entity entity;

	uint32_t                srbm_soft_reset;

};

/*

 * VCE

 */

#define AMDGPU_MAX_VCE_HANDLES	16

#define AMDGPU_VCE_FIRMWARE_OFFSET 256

#define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)

#define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)

struct amdgpu_vce {

	struct amdgpu_bo	*vcpu_bo;

	uint64_t		gpu_addr;

	unsigned		fw_version;

	unsigned		fb_version;

	atomic_t		handles[AMDGPU_MAX_VCE_HANDLES];

	struct drm_file		*filp[AMDGPU_MAX_VCE_HANDLES];

	uint32_t		img_size[AMDGPU_MAX_VCE_HANDLES];

	struct delayed_work	idle_work;

	struct mutex		idle_mutex;

	const struct firmware	*fw;	/* VCE firmware */

	struct amdgpu_ring	ring[AMDGPU_MAX_VCE_RINGS];

	struct amdgpu_irq_src	irq;

	unsigned		harvest_config;

	struct amd_sched_entity	entity;

	uint32_t                srbm_soft_reset;

	unsigned		num_rings;

};

/*

 * SDMA

 */

/*

 * Firmware

 */

enum amdgpu_firmware_load_type {

	AMDGPU_FW_LOAD_DIRECT = 0,

	AMDGPU_FW_LOAD_SMU,

	AMDGPU_FW_LOAD_PSP,

};

struct amdgpu_firmware {

	struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];

	bool smu_load;

	enum amdgpu_firmware_load_type load_type;

	struct amdgpu_bo *fw_buf;

	unsigned int fw_size;

	unsigned int max_ucodes;

	/* firmwares are loaded by psp instead of smu from vega10 */

	const struct amdgpu_psp_funcs *funcs;

	struct amdgpu_bo *rbuf;

	struct mutex mutex;

};

/*

 * Testing

 */

void amdgpu_test_moves(struct amdgpu_device *adev);

void amdgpu_test_ring_sync(struct amdgpu_device *adev,

			   struct amdgpu_ring *cpA,

			   struct amdgpu_ring *cpB);

void amdgpu_test_syncing(struct amdgpu_device *adev);

/*

 * MMU Notifier

	/* static power management */

	int (*get_pcie_lanes)(struct amdgpu_device *adev);

	void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);

	/* get config memsize register */

	u32 (*get_config_memsize)(struct amdgpu_device *adev);

};

/*

	bool				have_disp_power_ref;

	/* BIOS */

	bool				is_atom_fw;

	uint8_t				*bios;

	uint32_t			bios_size;

	struct amdgpu_bo		*stollen_vga_memory;

	uint32_t			bios_scratch_reg_offset;

	uint32_t			bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];

	/* Register/doorbell mmio */

	struct amdgpu_gart		gart;

	struct amdgpu_dummy_page	dummy_page;

	struct amdgpu_vm_manager	vm_manager;

	struct amdgpu_vmhub             vmhub[AMDGPU_MAX_VMHUBS];

	/* memory management */

	struct amdgpu_mman		mman;

	/* firmwares */

	struct amdgpu_firmware		firmware;

	/* PSP */

	struct psp_context		psp;

	/* GDS */

	struct amdgpu_gds		gds;

int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);

uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,

			bool always_indirect);

			uint32_t acc_flags);

void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,

		    bool always_indirect);

		    uint32_t acc_flags);

u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);

u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);

void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);

u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);

void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);

/*

 * Registers read & write functions.

 */

#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)

#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)

#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)

#define AMDGPU_REGS_IDX       (1<<0)

#define AMDGPU_REGS_NO_KIQ    (1<<1)

#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)

#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)

#define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)

#define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)

#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))

#define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)

#define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)

#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)

#define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))

#define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))

#define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))

#define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))

#define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))

#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK

{

	if (ring->count_dw <= 0)

		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	ring->ring[ring->wptr++] = v;

	ring->ring[ring->wptr++ & ring->buf_mask] = v;

	ring->wptr &= ring->ptr_mask;

	ring->count_dw--;

}

	if (ring->count_dw < count_dw) {

		DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");

	} else {

		occupied = ring->wptr & ring->ptr_mask;

		occupied = ring->wptr & ring->buf_mask;

		dst = (void *)&ring->ring[occupied];

		chunk1 = ring->ptr_mask + 1 - occupied;

		chunk1 = ring->buf_mask + 1 - occupied;

		chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;

		chunk2 = count_dw - chunk1;

		chunk1 <<= 2;

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))

#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))

#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))

#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))

#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))

#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))

#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))

#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))

#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))

/* Common functions */

int amdgpu_gpu_reset(struct amdgpu_device *adev);

bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,

				       int *last_invalidated);

bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);

uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,

uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,

				 struct ttm_mem_reg *mem);

void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);

void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);

int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);

void amdgpu_driver_postclose_kms(struct drm_device *dev,

				 struct drm_file *file_priv);

void amdgpu_driver_preclose_kms(struct drm_device *dev,

				struct drm_file *file_priv);

int amdgpu_suspend(struct amdgpu_device *adev);

int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);

int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);

	/* Check that we are in spec (not always possible) */

	if (n < (128*freq/1500))

		printk(KERN_WARNING "Calculated ACR N value is too small. You may experience audio problems.\n");

		pr_warn("Calculated ACR N value is too small. You may experience audio problems.\n");

	if (n > (128*freq/300))

		printk(KERN_WARNING "Calculated ACR N value is too large. You may experience audio problems.\n");

		pr_warn("Calculated ACR N value is too large. You may experience audio problems.\n");

	*N = n;

	*CTS = cts;

	memcpy(dst, src, num_bytes);

#endif

}

int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev)

{

	struct atom_context *ctx = adev->mode_info.atom_context;

	int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware);

	uint16_t data_offset;

	int usage_bytes = 0;

	struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage;

	if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {

		firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);

		DRM_DEBUG("atom firmware requested %08x %dkb\n",

			  le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),

			  le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));

		usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;

	}

	ctx->scratch_size_bytes = 0;

	if (usage_bytes == 0)

		usage_bytes = 20 * 1024;

	/* allocate some scratch memory */

	ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);

	if (!ctx->scratch)

		return -ENOMEM;

	ctx->scratch_size_bytes = usage_bytes;

	return 0;

}

int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev,

			      u8 voltage_type,

			      u8 *svd_gpio_id, u8 *svc_gpio_id);

int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev);

#endif