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Commit 8ab8b3e1 authored by Pranith Kumar's avatar Pranith Kumar Committed by Paul E. McKenney
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documentation: memory-barriers.txt: Correct example for reorderings 



Correct the example of memory orderings in memory-barriers.txt

Commit 615cc2c9 "Documentation/memory-barriers.txt: fix important typo re
memory barriers" changed the assignment to x and y. Change the rest of the
example to match this change.

Reported-by: default avatarGanesh Rapolu <ganesh.rapolu@hotmail.com>
Signed-off-by: default avatarPranith Kumar <bobby.prani@gmail.com>
Signed-off-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
parent 1f7870dd

Documentation/memory-barriers.txt

+11 −11
Original line number Diff line number Diff line
@@ -121,22 +121,22 @@ For example, consider the following sequence of events: 
The set of accesses as seen by the memory system in the middle can be arranged

in 24 different combinations:



	STORE A=3,	STORE B=4,	x=LOAD A->3,	y=LOAD B->4

	STORE A=3,	STORE B=4,	y=LOAD B->4,	x=LOAD A->3

	STORE A=3,	x=LOAD A->3,	STORE B=4,	y=LOAD B->4

	STORE A=3,	x=LOAD A->3,	y=LOAD B->2,	STORE B=4

	STORE A=3,	y=LOAD B->2,	STORE B=4,	x=LOAD A->3

	STORE A=3,	y=LOAD B->2,	x=LOAD A->3,	STORE B=4

	STORE B=4,	STORE A=3,	x=LOAD A->3,	y=LOAD B->4

	STORE A=3,	STORE B=4,	y=LOAD A->3,	x=LOAD B->4

	STORE A=3,	STORE B=4,	x=LOAD B->4,	y=LOAD A->3

	STORE A=3,	y=LOAD A->3,	STORE B=4,	x=LOAD B->4

	STORE A=3,	y=LOAD A->3,	x=LOAD B->2,	STORE B=4

	STORE A=3,	x=LOAD B->2,	STORE B=4,	y=LOAD A->3

	STORE A=3,	x=LOAD B->2,	y=LOAD A->3,	STORE B=4

	STORE B=4,	STORE A=3,	y=LOAD A->3,	x=LOAD B->4

	STORE B=4, ...

	...



and can thus result in four different combinations of values:



	x == 1, y == 2

	x == 1, y == 4

	x == 3, y == 2

	x == 3, y == 4

	x == 2, y == 1

	x == 2, y == 3

	x == 4, y == 1

	x == 4, y == 3





Furthermore, the stores committed by a CPU to the memory system may not be