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Commit 8a81dccd authored by Manjunathappa, Prakash's avatar Manjunathappa, Prakash Committed by Florian Tobias Schandinat
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video: da8xx-fb rev2: fix disabling of palette completion interrupt 



Writing '1' to particular bit of IRQENABLE_CLEAR register disables the
corresponding interrupt on revision 2 LCDC. This register was wrongly
configured to disable all previous enabled interrupts instead of
disabling only palette completion interrupt. Patch fixes it by clearing
only palette completion interrupt bit.

Signed-off-by: default avatarManjunathappa, Prakash <prakash.pm@ti.com>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent 99a647d1

drivers/video/da8xx-fb.c

+2 −5
Original line number Original line Diff line number Diff line
@@ -716,7 +716,6 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) 
{

{

	struct da8xx_fb_par *par = arg;

	struct da8xx_fb_par *par = arg;

	u32 stat = lcdc_read(LCD_MASKED_STAT_REG);

	u32 stat = lcdc_read(LCD_MASKED_STAT_REG);

	u32 reg_int;





	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

	if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {

		lcd_disable_raster();

		lcd_disable_raster();
@@ -733,10 +732,8 @@ static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg) 




		lcdc_write(stat, LCD_MASKED_STAT_REG);

		lcdc_write(stat, LCD_MASKED_STAT_REG);





		/* Disable PL completion inerrupt */

		/* Disable PL completion interrupt */

		reg_int = lcdc_read(LCD_INT_ENABLE_CLR_REG) |

		lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);

		       (LCD_V2_PL_INT_ENA);

		lcdc_write(reg_int, LCD_INT_ENABLE_CLR_REG);





		/* Setup and start data loading mode */

		/* Setup and start data loading mode */

		lcd_blit(LOAD_DATA, par);

		lcd_blit(LOAD_DATA, par);