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Commit 899f6204 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/execlists: Split the atomic test_and_clear_bit for irq handler 



Rather than impose the cost of a locked test before queuing a new
request, reduce it to a simple test_bit() with a following clear_bit()
prior to doing the CSB check. This ensure that if an interrupt does
occur whilst reading from the CSB, we still detect it (the interrupt
would trigger a rescheduling of the tasklet anyway).

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170321113320.2603-1-chris@chris-wilson.co.uk


Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent 272bce17

drivers/gpu/drm/i915/intel_lrc.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -530,13 +530,18 @@ static void intel_lrc_irq_handler(unsigned long data) 




	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);

	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);





	while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {

	/* Prefer doing test_and_clear_bit() as a two stage operation to avoid

	 * imposing the cost of a locked atomic transaction when submitting a

	 * new request (outside of the context-switch interrupt).

	 */

	while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {

		u32 __iomem *csb_mmio =

		u32 __iomem *csb_mmio =

			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));

			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));

		u32 __iomem *buf =

		u32 __iomem *buf =

			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));

			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));

		unsigned int csb, head, tail;

		unsigned int csb, head, tail;





		clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);

		csb = readl(csb_mmio);

		csb = readl(csb_mmio);

		head = GEN8_CSB_READ_PTR(csb);

		head = GEN8_CSB_READ_PTR(csb);

		tail = GEN8_CSB_WRITE_PTR(csb);

		tail = GEN8_CSB_WRITE_PTR(csb);