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Commit 892204e0 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips 

Pull MIPS updates from James Hogan:
 "These are the main MIPS changes for 4.15.

  Fixes:
   - ralink: Fix MT7620 PCI build issues (4.5)
   - Disable cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN for 32-bit SMP
     (4.1)
   - Fix MIPS64 FP save/restore on 32-bit kernels (4.0)
   - ptrace: Pick up ptrace/seccomp changed syscall numbers (3.19)
   - ralink: Fix MT7628 pinmux (3.19)
   - BCM47XX: Fix LED inversion on WRT54GSv1 (3.17)
   - Fix n32 core dumping as o32 since regset support (3.13)
   - ralink: Drop obsolete USB_ARCH_HAS_HCD select

  Build system:
   - Default to "generic" (multiplatform) system type instead of IP22
   - Use generic little endian MIPS32 r2 configuration as default
     defconfig instead of ip22_defconfig

  FPU emulation:
   - Fix exception generation for certain R6 FPU instructions

  SMP:
   - Allow __cpu_number_map to be larger than NR_CPUS for sparse CPU id
     spaces

  Miscellaneous:
   - Add iomem resource for kernel bss section for kexec/kdump
   - Atomics: Nudge writes on bit unlock
   - DT files: Standardise "ok" -> "okay"

  Minor cleanups:
   - Define virt_to_pfn()
   - Make thread_saved_pc static
   - Simplify 32-bit sign extension in __read_64bit_c0_split()
   - DMA: Use vma_pages() helper
   - FPU emulation: Replace unsigned with unsigned int
   - MM: Removed unused lastpfn
   - Alchemy: Make clk_ops const
   - Lasat: Use setup_timer() helper
   - ralink: Use BIT() in MT7620 PCI driver

  Platform support:

  BMIPS:
  - Enable HARDIRQS_SW_RESEND

  Broadcom BCM63XX:
  - Add clkdev lookup support
  - Update clk driver, UART driver, DTs to handle named refclk from DTs
  - Split apart various clocks to more closely match hardware
  - Add ethernet clocks

  Cavium Octeon:
  - Remove usage of cvmx_wait() in favour of __delay()

  ImgTec Pistachio:
  - DT: Drop deprecated dwmmc num-slots property

  Ingenic JZ4780:
  - Add NFS root to Ci20 defconfig
  - Add watchdog to Ci20 DT & defconfig, and allow building of watchdog
    driver with this SoC

  Generic (multiplatform):
  - Migrate xilfpga (MIPSfpga) platform to the generic platform

  Lantiq xway:
  - Fix ASC0/ASC1 clocks"

* tag 'mips_4.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (46 commits)
  MIPS: Add iomem resource for kernel bss section.
  MIPS: cmpxchg64() and HAVE_VIRT_CPU_ACCOUNTING_GEN don't work for 32-bit SMP
  MIPS: BMIPS: Enable HARDIRQS_SW_RESEND
  MIPS: pci: Make use of the BIT() macro inside the mt7620 driver
  MIPS: pci: Remove KERN_WARN instance inside the mt7620 driver
  MIPS: pci: Remove duplicate define in mt7620 driver
  MIPS: ralink: Fix typo in mt7628 pinmux function
  MIPS: ralink: Fix MT7628 pinmux
  MIPS: Fix odd fp register warnings with MIPS64r2
  watchdog: jz4780: Allow selection of jz4740-wdt driver
  MIPS/ptrace: Update syscall nr on register changes
  MIPS/ptrace: Pick up ptrace/seccomp changed syscalls
  MIPS: Fix an n32 core file generation regset support regression
  MIPS: Fix MIPS64 FP save/restore on 32-bit kernels
  MIPS: page.h: Define virt_to_pfn()
  MIPS: Xilfpga: Switch to using generic defconfigs
  MIPS: generic: Add support for MIPSfpga
  MIPS: Set defconfig target to a generic system for 32r2el
  MIPS: Kconfig: Set default MIPS system type as generic
  MIPS: DTS: Remove num-slots from Pistachio SoC
  ...
parents c9b012e5 e0c5f36b

Documentation/devicetree/bindings/serial/brcm,bcm6345-uart.txt

+6 −0
Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ Required properties: 
- clocks: Clock driving the hardware; used to figure out the baud rate

  divisor.





Optional properties:



- clock-names: Should be "refclk".



Example:



	uart0: serial@14e00520 {
@@ -19,6 +24,7 @@ Example: 
		interrupt-parent = <&periph_intc>;

		interrupts = <2>;

		clocks = <&periph_clk>;

		clock-names = "refclk";

	};



	clocks {

arch/mips/Kbuild.platforms

+0 −1
Original line number Diff line number Diff line
@@ -34,7 +34,6 @@ platforms += sibyte 
platforms += sni

platforms += txx9

platforms += vr41xx

platforms += xilfpga



# include the platform specific files

include $(patsubst %, $(srctree)/arch/mips/%/Platform, $(platforms))

arch/mips/Kconfig

+15 −27
Original line number Diff line number Diff line
@@ -65,7 +65,7 @@ config MIPS 
	select HAVE_PERF_EVENTS

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_SYSCALL_TRACEPOINTS

	select HAVE_VIRT_CPU_ACCOUNTING_GEN

	select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP

	select IRQ_FORCED_THREADING

	select MODULES_USE_ELF_RELA if MODULES && 64BIT

	select MODULES_USE_ELF_REL if MODULES
@@ -78,7 +78,7 @@ menu "Machine selection" 


choice

	prompt "System type"

	default SGI_IP22

	default MIPS_GENERIC



config MIPS_GENERIC

	bool "Generic board-agnostic MIPS kernel"
@@ -233,6 +233,7 @@ config BMIPS_GENERIC 
	select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN

	select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN

	select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN

	select HARDIRQS_SW_RESEND

	help

	  Build a generic DT-based kernel image that boots on select

	  BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
@@ -276,6 +277,7 @@ config BCM63XX 
	select GPIOLIB

	select HAVE_CLK

	select MIPS_L1_CACHE_SHIFT_4

	select CLKDEV_LOOKUP

	help

	 Support for BCM63XX based boards
@@ -468,29 +470,6 @@ config MACH_PISTACHIO 
	help

	  This enables support for the IMG Pistachio SoC platform.



config MACH_XILFPGA

	bool "MIPSfpga Xilinx based boards"

	select BOOT_ELF32

	select BOOT_RAW

	select BUILTIN_DTB

	select CEVT_R4K

	select COMMON_CLK

	select CSRC_R4K

	select GPIOLIB

	select IRQ_MIPS_CPU

	select LIBFDT

	select MIPS_CPU_SCACHE

	select SYS_HAS_EARLY_PRINTK

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_ZBOOT_UART16550

	select USE_OF

	select USE_GENERIC_EARLY_PRINTK_8250

	select XILINX_INTC

	help

	  This enables support for the IMG University Program MIPSfpga platform.



config MIPS_MALTA

	bool "MIPS Malta board"

	select ARCH_MAY_HAVE_PC_FDC
@@ -916,7 +895,8 @@ config CAVIUM_OCTEON_SOC 
	select USE_OF

	select ARCH_SPARSEMEM_ENABLE

	select SYS_SUPPORTS_SMP

	select NR_CPUS_DEFAULT_16

	select NR_CPUS_DEFAULT_64

	select MIPS_NR_CPU_NR_MAP_1024

	select BUILTIN_DTB

	select MTD_COMPLEX_MAPPINGS

	select SYS_SUPPORTS_RELOCATABLE
@@ -1034,7 +1014,6 @@ source "arch/mips/loongson32/Kconfig" 
source "arch/mips/loongson64/Kconfig"

source "arch/mips/netlogic/Kconfig"

source "arch/mips/paravirt/Kconfig"

source "arch/mips/xilfpga/Kconfig"



endmenu
@@ -2726,6 +2705,15 @@ config NR_CPUS 
config MIPS_PERF_SHARED_TC_COUNTERS

	bool



config MIPS_NR_CPU_NR_MAP_1024

	bool



config MIPS_NR_CPU_NR_MAP

	int

	depends on SMP

	default 1024 if MIPS_NR_CPU_NR_MAP_1024

	default NR_CPUS if !MIPS_NR_CPU_NR_MAP_1024



#

# Timer Interrupt Frequency Configuration

#

arch/mips/Makefile

+5 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
archscripts: scripts_basic

	$(Q)$(MAKE) $(build)=arch/mips/boot/tools relocs



KBUILD_DEFCONFIG := ip22_defconfig

KBUILD_DEFCONFIG := 32r2el_defconfig



#

# Select the object file format to substitute into the linker script.
@@ -544,3 +544,7 @@ sead3_defconfig: 
.PHONY: sead3micro_defconfig

sead3micro_defconfig:

	$(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3



.PHONY: xilfpga_defconfig

xilfpga_defconfig:

	$(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga

arch/mips/alchemy/common/clock.c

+5 −5
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ void __init alchemy_set_lpj(void) 
	preset_lpj /= 2 * HZ;

}



static struct clk_ops alchemy_clkops_cpu = {

static const struct clk_ops alchemy_clkops_cpu = {

	.recalc_rate	= alchemy_clk_cpu_recalc,

};
@@ -224,7 +224,7 @@ static long alchemy_clk_aux_roundr(struct clk_hw *hw, 
	return (*parent_rate) * mult;

}



static struct clk_ops alchemy_clkops_aux = {

static const struct clk_ops alchemy_clkops_aux = {

	.recalc_rate	= alchemy_clk_aux_recalc,

	.set_rate	= alchemy_clk_aux_setr,

	.round_rate	= alchemy_clk_aux_roundr,
@@ -576,7 +576,7 @@ static int alchemy_clk_fgv1_detr(struct clk_hw *hw, 
}



/* Au1000, Au1100, Au15x0, Au12x0 */

static struct clk_ops alchemy_clkops_fgenv1 = {

static const struct clk_ops alchemy_clkops_fgenv1 = {

	.recalc_rate	= alchemy_clk_fgv1_recalc,

	.determine_rate	= alchemy_clk_fgv1_detr,

	.set_rate	= alchemy_clk_fgv1_setr,
@@ -717,7 +717,7 @@ static int alchemy_clk_fgv2_detr(struct clk_hw *hw, 
}



/* Au1300 larger input mux, no separate disable bit, flexible divider */

static struct clk_ops alchemy_clkops_fgenv2 = {

static const struct clk_ops alchemy_clkops_fgenv2 = {

	.recalc_rate	= alchemy_clk_fgv2_recalc,

	.determine_rate	= alchemy_clk_fgv2_detr,

	.set_rate	= alchemy_clk_fgv2_setr,
@@ -925,7 +925,7 @@ static int alchemy_clk_csrc_detr(struct clk_hw *hw, 
	return alchemy_clk_fgcs_detr(hw, req, scale, 4);

}



static struct clk_ops alchemy_clkops_csrc = {

static const struct clk_ops alchemy_clkops_csrc = {

	.recalc_rate	= alchemy_clk_csrc_recalc,

	.determine_rate	= alchemy_clk_csrc_detr,

	.set_rate	= alchemy_clk_csrc_setr,