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Commit 88f52ecd authored by Michael Turquette's avatar Michael Turquette
Browse files

Merge branch 'clk-shmobile-for-3.20' of... 

Merge branch 'clk-shmobile-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
parents 57386798 14842761

Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt

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@@ -11,6 +11,7 @@ Required Properties: 


  - compatible: Must be one of the following

    - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks

    - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks

    - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks

    - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks

    - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks

Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt

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* Renesas R8A73A4 Clock Pulse Generator (CPG)



The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs

and several fixed ratio dividers.



Required Properties:



  - compatible: Must be "renesas,r8a73a4-cpg-clocks"



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: Reference to the parent clocks ("extal1" and "extal2")



  - #clock-cells: Must be 1



  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",

    "m1", "m2", "zx", "zs", and "hp".





Example

-------



        cpg_clocks: cpg_clocks@e6150000 {

                compatible = "renesas,r8a73a4-cpg-clocks";

                reg = <0 0xe6150000 0 0x10000>;

                clocks = <&extal1_clk>, <&extal2_clk>;

                #clock-cells = <1>;

                clock-output-names = "main", "pll0", "pll1", "pll2",

                                     "pll2s", "pll2h", "z", "z2",

                                     "i", "m3", "b", "m1", "m2",

                                     "zx", "zs", "hp";

        };

Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt

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@@ -8,15 +8,18 @@ Required Properties: 
  - compatible: Must be one of

    - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG

    - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG

    - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG

    - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG

    - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG



  - reg: Base address and length of the memory resource used by the CPG



  - clocks: Reference to the parent clock

  - clocks: References to the parent clocks: first to the EXTAL clock, second

    to the USB_EXTAL clock

  - #clock-cells: Must be 1

  - clock-output-names: The names of the clocks. Supported clocks are "main",

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z"

    "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and

    "adsp"





Example
@@ -26,8 +29,9 @@ Example 
		compatible = "renesas,r8a7790-cpg-clocks",

			     "renesas,rcar-gen2-cpg-clocks";

		reg = <0 0xe6150000 0 0x1000>;

		clocks = <&extal_clk>;

		clocks = <&extal_clk &usb_extal_clk>;

		#clock-cells = <1>;

		clock-output-names = "main", "pll0, "pll1", "pll3",

				     "lb", "qspi", "sdh", "sd0", "sd1", "z";

				     "lb", "qspi", "sdh", "sd0", "sd1", "z",

				     "rcan", "adsp";

	};

drivers/clk/shmobile/Makefile

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obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o

obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o

obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o

obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o

obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o

obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o

obj-$(CONFIG_ARCH_R8A7791)		+= clk-rcar-gen2.o

obj-$(CONFIG_ARCH_R8A7793)		+= clk-rcar-gen2.o

obj-$(CONFIG_ARCH_R8A7794)		+= clk-rcar-gen2.o

obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-div6.o

obj-$(CONFIG_ARCH_SHMOBILE_MULTI)	+= clk-mstp.o

drivers/clk/shmobile/clk-div6.c

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@@ -54,12 +54,19 @@ static int cpg_div6_clock_enable(struct clk_hw *hw) 
static void cpg_div6_clock_disable(struct clk_hw *hw)

{

	struct div6_clock *clock = to_div6_clock(hw);

	u32 val;



	/* DIV6 clocks require the divisor field to be non-zero when stopping

	 * the clock.

	val = clk_readl(clock->reg);

	val |= CPG_DIV6_CKSTP;

	/*

	 * DIV6 clocks require the divisor field to be non-zero when stopping

	 * the clock. However, some clocks (e.g. ZB on sh73a0) fail to be

	 * re-enabled later if the divisor field is changed when stopping the

	 * clock

	 */

	clk_writel(clk_readl(clock->reg) | CPG_DIV6_CKSTP | CPG_DIV6_DIV_MASK,

		   clock->reg);

	if (!(val & CPG_DIV6_DIV_MASK))

		val |= CPG_DIV6_DIV_MASK;

	clk_writel(val, clock->reg);

}



static int cpg_div6_clock_is_enabled(struct clk_hw *hw)