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Commit 88560100 authored by Javier Martinez Canillas's avatar Javier Martinez Canillas Committed by Kukjin Kim
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clk: exynos5420: Add IDs for clocks used in DISP1 power domain 



When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.

Signed-off-by: default avatarJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: default avatarMichael Turquette <mturquette@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene@kernel.org>
parent 6591a02e

drivers/clk/samsung/clk-exynos5420.c

+12 −11
Original line number Diff line number Diff line
@@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
			SRC_TOP3, 0, 1),

	MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,

			SRC_TOP3, 4, 1),

	MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,

			SRC_TOP3, 8, 1),

	MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",

			mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),

	MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,

			SRC_TOP3, 12, 1),

	MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
@@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
	MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,

			SRC_TOP4, 28, 1),



	MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,

			SRC_TOP5, 0, 1),

	MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",

			mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),

	MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,

			SRC_TOP5, 4, 1),

	MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
@@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
			SRC_TOP5, 16, 1),

	MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,

			SRC_TOP5, 20, 1),

	MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,

			SRC_TOP5, 24, 1),

	MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",

			mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),

	MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,

			SRC_TOP5, 28, 1),
@@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
			SRC_TOP10, 0, 1),

	MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,

			SRC_TOP10, 4, 1),

	MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),

	MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,

			SRC_TOP10, 8, 1),

	MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,

			SRC_TOP10, 12, 1),

	MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
@@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
	MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,

			SRC_TOP11, 28, 1),



	MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,

			SRC_TOP12, 4, 1),

	MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",

			mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),

	MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,

			SRC_TOP12, 8, 1),

	MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
@@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = { 
	MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),

	MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,

			SRC_TOP12, 20, 1),

	MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,

			SRC_TOP12, 24, 1),

	MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",

			mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),

	MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,

			SRC_TOP12, 28, 1),

include/dt-bindings/clock/exynos5420.h

+6 −0
Original line number Diff line number Diff line
@@ -204,6 +204,12 @@ 
#define CLK_MOUT_MAUDIO0	643

#define CLK_MOUT_USER_ACLK333	644

#define CLK_MOUT_SW_ACLK333	645

#define CLK_MOUT_USER_ACLK200_DISP1	646

#define CLK_MOUT_SW_ACLK200	647

#define CLK_MOUT_USER_ACLK300_DISP1     648

#define CLK_MOUT_SW_ACLK300     649

#define CLK_MOUT_USER_ACLK400_DISP1     650

#define CLK_MOUT_SW_ACLK400     651



/* divider clocks */

#define CLK_DOUT_PIXEL		768