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Commit 883992bd authored by Paul Walmsley's avatar Paul Walmsley Committed by Russell King
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[ARM] OMAP2/3 clock: don't tinker with hardirqs when they are supposed to be disabled 



Clock rate change code executes inside a spinlock with hardirqs
disabled.  The only code that should be messing around with the
hardirq state should be the plat-omap/clock.c code.  In the
omap2_reprogram_dpllcore() case, this probably just wastes cycles, but
in the omap3_core_dpll_m2_set_rate() case, this is a nasty bug.

linux-omap source commit is b9b6208dadb5e0d8b290900a3ffa911673ca97ed.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 8263e5b3

arch/arm/mach-omap2/clock24xx.c

+3 −9
Original line number Diff line number Diff line
@@ -380,10 +380,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
	u32 bypass = 0;

	struct prcm_config tmpset;

	const struct dpll_data *dd;

	unsigned long flags;

	int ret = -EINVAL;



	local_irq_save(flags);

	cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck);

	mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2);

	mult &= OMAP24XX_CORE_CLK_SRC_MASK;
@@ -395,7 +392,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
	} else if (rate != cur_rate) {

		valid_rate = omap2_dpllcore_round_rate(rate);

		if (valid_rate != rate)

			goto dpll_exit;

			return -EINVAL;



		if (mult == 1)

			low = curr_prcm_set->dpll_speed;
@@ -404,7 +401,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 


		dd = clk->dpll_data;

		if (!dd)

			goto dpll_exit;

			return -EINVAL;



		tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);

		tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
@@ -441,11 +438,8 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) 
		omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked());

		omap2xxx_sdrc_reprogram(done_rate, 0);

	}

	ret = 0;



dpll_exit:

	local_irq_restore(flags);

	return(ret);

	return 0;

}



/**

arch/arm/mach-omap2/clock34xx.c

+0 −2
Original line number Diff line number Diff line
@@ -686,10 +686,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) 
	WARN_ON(new_div != 1 && new_div != 2);



	/* REVISIT: Add SDRC_MR changing to this code also */

	local_irq_disable();

	omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,

				  sp->actim_ctrlb, new_div);

	local_irq_enable();



	return 0;

}