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Commit 8652744b authored by Tvrtko Ursulin's avatar Tvrtko Ursulin
Browse files

drm/i915: Make IS_BROADWELL only take dev_priv



Saves 1808 bytes of .rodata strings.

v2: Add parantheses around dev_priv. (Ville Syrjala)

Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Acked-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: default avatarJani Nikula <jani.nikula@linux.intel.com>
Acked-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Acked-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
parent fd6b8f43
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+4 −2
Original line number Diff line number Diff line
@@ -189,13 +189,15 @@ static void intel_detect_pch(struct drm_device *dev)
			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
				WARN_ON(IS_HSW_ULT(dev_priv) ||
					IS_BDW_ULT(dev_priv));
			} else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
				dev_priv->pch_type = PCH_LPT;
				DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
				WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
				WARN_ON(!IS_HASWELL(dev_priv) &&
					!IS_BROADWELL(dev_priv));
				WARN_ON(!IS_HSW_ULT(dev_priv) &&
					!IS_BDW_ULT(dev_priv));
			} else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
+3 −3
Original line number Diff line number Diff line
@@ -2658,7 +2658,7 @@ struct drm_i915_cmd_table {
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->is_broadwell)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.is_broadwell)
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
@@ -2765,8 +2765,8 @@ struct drm_i915_cmd_table {
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
				 HAS_EDRAM(dev))
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
#define HWS_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->hws_needs_physical)

#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
+3 −2
Original line number Diff line number Diff line
@@ -3480,7 +3480,7 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
		level = I915_CACHE_LLC;
		break;
	case I915_CACHING_DISPLAY:
		level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
		level = HAS_WT(dev_priv) ? I915_CACHE_WT : I915_CACHE_NONE;
		break;
	default:
		return -EINVAL;
@@ -3538,7 +3538,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
	 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
	 */
	ret = i915_gem_object_set_cache_level(obj,
					      HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
					      HAS_WT(to_i915(obj->base.dev)) ?
					      I915_CACHE_WT : I915_CACHE_NONE);
	if (ret) {
		vma = ERR_PTR(ret);
		goto err_unpin_display;
+1 −1
Original line number Diff line number Diff line
@@ -2131,7 +2131,7 @@ static void gtt_write_workarounds(struct drm_device *dev)
	 * workarounds here even if they get overwritten by GPU reset.
	 */
	/* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
	if (IS_BROADWELL(dev))
	if (IS_BROADWELL(dev_priv))
		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
	else if (IS_CHERRYVIEW(dev))
		I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
+2 −2
Original line number Diff line number Diff line
@@ -540,8 +540,8 @@ void intel_color_init(struct drm_crtc *crtc)
	} else if (IS_HASWELL(dev)) {
		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
		dev_priv->display.load_luts = haswell_load_luts;
	} else if (IS_BROADWELL(dev) || IS_SKYLAKE(dev) ||
		   IS_BROXTON(dev) || IS_KABYLAKE(dev)) {
	} else if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) ||
		   IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) {
		dev_priv->display.load_csc_matrix = i9xx_load_csc_matrix;
		dev_priv->display.load_luts = broadwell_load_luts;
	} else {
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