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Commit 863018a7 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

m32r: Cleanup direct irq_desc access 



The irq descriptors are already initialized by the generic
code. Remove the redundant init code and set the irq chip with the
proper accessor function.

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: Paul Mundt <lethal@linux-sh.org>
parent 30139785

arch/m32r/kernel/irq.c

+6 −4
Original line number Diff line number Diff line
@@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v) 
	}



	if (i < NR_IRQS) {

		raw_spin_lock_irqsave(&irq_desc[i].lock, flags);

		action = irq_desc[i].action;

		struct irq_desc *desc = irq_to_desc(i);



		raw_spin_lock_irqsave(&desc->lock, flags);

		action = desc->action;

		if (!action)

			goto skip;

		seq_printf(p, "%3d: ",i);
@@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v) 
		for_each_online_cpu(j)

			seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));

#endif

		seq_printf(p, " %14s", irq_desc[i].chip->name);

		seq_printf(p, " %14s", desc->irq_data.chip->name);

		seq_printf(p, "  %s", action->name);



		for (action=action->next; action; action = action->next)
@@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v) 


		seq_putc(p, '\n');

skip:

		raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);

		raw_spin_unlock_irqrestore(&desc->lock, flags);

	}

	return 0;

}

arch/m32r/platforms/m32104ut/setup.c

+4 −16
Original line number Diff line number Diff line
@@ -85,36 +85,24 @@ void __init init_IRQ(void) 


#if defined(CONFIG_SMC91X)

	/* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/

	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type;

	irq_desc[M32R_IRQ_INT0].action = 0;

	irq_desc[M32R_IRQ_INT0].depth = 1;

	set_irq_chip(M32R_IRQ_INT0, &m32104ut_irq_type);

	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */

	disable_m32104ut_irq(M32R_IRQ_INT0);

#endif  /* CONFIG_SMC91X */



	/* MFT2 : system timer */

	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type;

	irq_desc[M32R_IRQ_MFT2].action = 0;

	irq_desc[M32R_IRQ_MFT2].depth = 1;

	set_irq_chip(M32R_IRQ_MFT2, &m32104ut_irq_type);

	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;

	disable_m32104ut_irq(M32R_IRQ_MFT2);



#ifdef CONFIG_SERIAL_M32R_SIO

	/* SIO0_R : uart receive data */

	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type;

	irq_desc[M32R_IRQ_SIO0_R].action = 0;

	irq_desc[M32R_IRQ_SIO0_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_R, &m32104ut_irq_type);

	icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;

	disable_m32104ut_irq(M32R_IRQ_SIO0_R);



	/* SIO0_S : uart send data */

	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type;

	irq_desc[M32R_IRQ_SIO0_S].action = 0;

	irq_desc[M32R_IRQ_SIO0_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_S, &m32104ut_irq_type);

	icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;

	disable_m32104ut_irq(M32R_IRQ_SIO0_S);

#endif /* CONFIG_SERIAL_M32R_SIO */

arch/m32r/platforms/m32700ut/setup.c

+16 −58
Original line number Diff line number Diff line
@@ -299,101 +299,65 @@ void __init init_IRQ(void) 
{

#if defined(CONFIG_SMC91X)

	/* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/

	irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED;

	irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type;

	irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;

	irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1;	/* disable nested irq */

	set_irq_chip(M32700UT_LAN_IRQ_LAN, &m32700ut_lanpld_irq_type);

	lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* "H" edge sense */

	disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);

#endif  /* CONFIG_SMC91X */



	/* MFT2 : system timer */

	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_MFT2].action = 0;

	irq_desc[M32R_IRQ_MFT2].depth = 1;

	set_irq_chip(M32R_IRQ_MFT2, &m32700ut_irq_type);

	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;

	disable_m32700ut_irq(M32R_IRQ_MFT2);



	/* SIO0 : receive */

	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_SIO0_R].action = 0;

	irq_desc[M32R_IRQ_SIO0_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_R, &m32700ut_irq_type);

	icu_data[M32R_IRQ_SIO0_R].icucr = 0;

	disable_m32700ut_irq(M32R_IRQ_SIO0_R);



	/* SIO0 : send */

	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_SIO0_S].action = 0;

	irq_desc[M32R_IRQ_SIO0_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_S, &m32700ut_irq_type);

	icu_data[M32R_IRQ_SIO0_S].icucr = 0;

	disable_m32700ut_irq(M32R_IRQ_SIO0_S);



	/* SIO1 : receive */

	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_SIO1_R].action = 0;

	irq_desc[M32R_IRQ_SIO1_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_R, &m32700ut_irq_type);

	icu_data[M32R_IRQ_SIO1_R].icucr = 0;

	disable_m32700ut_irq(M32R_IRQ_SIO1_R);



	/* SIO1 : send */

	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_SIO1_S].action = 0;

	irq_desc[M32R_IRQ_SIO1_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_S, &m32700ut_irq_type);

	icu_data[M32R_IRQ_SIO1_S].icucr = 0;

	disable_m32700ut_irq(M32R_IRQ_SIO1_S);



	/* DMA1 : */

	irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_DMA1].action = 0;

	irq_desc[M32R_IRQ_DMA1].depth = 1;

	set_irq_chip(M32R_IRQ_DMA1, &m32700ut_irq_type);

	icu_data[M32R_IRQ_DMA1].icucr = 0;

	disable_m32700ut_irq(M32R_IRQ_DMA1);



#ifdef CONFIG_SERIAL_M32R_PLDSIO

	/* INT#1: SIO0 Receive on PLD */

	irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type;

	irq_desc[PLD_IRQ_SIO0_RCV].action = 0;

	irq_desc[PLD_IRQ_SIO0_RCV].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type);

	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;

	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);



	/* INT#1: SIO0 Send on PLD */

	irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type;

	irq_desc[PLD_IRQ_SIO0_SND].action = 0;

	irq_desc[PLD_IRQ_SIO0_SND].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type);

	pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;

	disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);

#endif  /* CONFIG_SERIAL_M32R_PLDSIO */



	/* INT#1: CFC IREQ on PLD */

	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type;

	irq_desc[PLD_IRQ_CFIREQ].action = 0;

	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type);

	pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* 'L' level sense */

	disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);



	/* INT#1: CFC Insert on PLD */

	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type;

	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;

	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type);

	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;	/* 'L' edge sense */

	disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);



	/* INT#1: CFC Eject on PLD */

	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type;

	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;

	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type);

	pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;	/* 'H' edge sense */

	disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
@@ -413,11 +377,8 @@ void __init init_IRQ(void) 


#if defined(CONFIG_USB)

	outw(USBCR_OTGS, USBCR); 	/* USBCR: non-OTG */

	set_irq_chip(M32700UT_LCD_IRQ_USB_INT1, &m32700ut_lcdpld_irq_type);



    irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED;

    irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type;

    irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;

    irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;

	lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;	/* "L" level sense */

	disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);

#endif
@@ -432,10 +393,7 @@ void __init init_IRQ(void) 
	/*

	 * INT3# is used for AR

	 */

	irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type;

	irq_desc[M32R_IRQ_INT3].action = 0;

	irq_desc[M32R_IRQ_INT3].depth = 1;

	set_irq_chip(M32R_IRQ_INT3, &m32700ut_irq_type);

	icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;

	disable_m32700ut_irq(M32R_IRQ_INT3);

#endif	/* CONFIG_VIDEO_M32R_AR */

arch/m32r/platforms/mappi/setup.c

+8 −33
Original line number Diff line number Diff line
@@ -45,7 +45,6 @@ static void mask_and_ack_mappi(unsigned int irq) 


static void end_mappi_irq(unsigned int irq)

{

	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))

		enable_mappi_irq(irq);

}
@@ -85,70 +84,46 @@ void __init init_IRQ(void) 


#ifdef CONFIG_NE2000

	/* INT0 : LAN controller (RTL8019AS) */

	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_INT0].action = NULL;

	irq_desc[M32R_IRQ_INT0].depth = 1;

	set_irq_chip(M32R_IRQ_INT0, &mappi_irq_type);

	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;

	disable_mappi_irq(M32R_IRQ_INT0);

#endif /* CONFIG_M32R_NE2000 */



	/* MFT2 : system timer */

	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_MFT2].action = NULL;

	irq_desc[M32R_IRQ_MFT2].depth = 1;

	set_irq_chip(M32R_IRQ_MFT2, &mappi_irq_type);

	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;

	disable_mappi_irq(M32R_IRQ_MFT2);



#ifdef CONFIG_SERIAL_M32R_SIO

	/* SIO0_R : uart receive data */

	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_SIO0_R].action = NULL;

	irq_desc[M32R_IRQ_SIO0_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_R, &mappi_irq_type);

	icu_data[M32R_IRQ_SIO0_R].icucr = 0;

	disable_mappi_irq(M32R_IRQ_SIO0_R);



	/* SIO0_S : uart send data */

	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_SIO0_S].action = NULL;

	irq_desc[M32R_IRQ_SIO0_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_S, &mappi_irq_type);

	icu_data[M32R_IRQ_SIO0_S].icucr = 0;

	disable_mappi_irq(M32R_IRQ_SIO0_S);



	/* SIO1_R : uart receive data */

	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_SIO1_R].action = NULL;

	irq_desc[M32R_IRQ_SIO1_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_R, &mappi_irq_type);

	icu_data[M32R_IRQ_SIO1_R].icucr = 0;

	disable_mappi_irq(M32R_IRQ_SIO1_R);



	/* SIO1_S : uart send data */

	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_SIO1_S].action = NULL;

	irq_desc[M32R_IRQ_SIO1_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_S, &mappi_irq_type);

	icu_data[M32R_IRQ_SIO1_S].icucr = 0;

	disable_mappi_irq(M32R_IRQ_SIO1_S);

#endif /* CONFIG_SERIAL_M32R_SIO */



#if defined(CONFIG_M32R_PCC)

	/* INT1 : pccard0 interrupt */

	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_INT1].action = NULL;

	irq_desc[M32R_IRQ_INT1].depth = 1;

	set_irq_chip(M32R_IRQ_INT1, &mappi_irq_type);

	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;

	disable_mappi_irq(M32R_IRQ_INT1);



	/* INT2 : pccard1 interrupt */

	irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type;

	irq_desc[M32R_IRQ_INT2].action = NULL;

	irq_desc[M32R_IRQ_INT2].depth = 1;

	set_irq_chip(M32R_IRQ_INT2, &mappi_irq_type);

	icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;

	disable_mappi_irq(M32R_IRQ_INT2);

#endif /* CONFIG_M32RPCC */

arch/m32r/platforms/mappi2/setup.c

+10 −40
Original line number Diff line number Diff line
@@ -85,87 +85,57 @@ void __init init_IRQ(void) 
{

#if defined(CONFIG_SMC91X)

	/* INT0 : LAN controller (SMC91111) */

	irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_INT0].action = 0;

	irq_desc[M32R_IRQ_INT0].depth = 1;

	set_irq_chip(M32R_IRQ_INT0, &mappi2_irq_type);

	icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;

	disable_mappi2_irq(M32R_IRQ_INT0);

#endif  /* CONFIG_SMC91X */



	/* MFT2 : system timer */

	irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_MFT2].action = 0;

	irq_desc[M32R_IRQ_MFT2].depth = 1;

	set_irq_chip(M32R_IRQ_MFT2, &mappi2_irq_type);

	icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;

	disable_mappi2_irq(M32R_IRQ_MFT2);



#ifdef CONFIG_SERIAL_M32R_SIO

	/* SIO0_R : uart receive data */

	irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_SIO0_R].action = 0;

	irq_desc[M32R_IRQ_SIO0_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_R, &mappi2_irq_type);

	icu_data[M32R_IRQ_SIO0_R].icucr = 0;

	disable_mappi2_irq(M32R_IRQ_SIO0_R);



	/* SIO0_S : uart send data */

	irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_SIO0_S].action = 0;

	irq_desc[M32R_IRQ_SIO0_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO0_S, &mappi2_irq_type);

	icu_data[M32R_IRQ_SIO0_S].icucr = 0;

	disable_mappi2_irq(M32R_IRQ_SIO0_S);

	/* SIO1_R : uart receive data */

	irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_SIO1_R].action = 0;

	irq_desc[M32R_IRQ_SIO1_R].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_R, &mappi2_irq_type);

	icu_data[M32R_IRQ_SIO1_R].icucr = 0;

	disable_mappi2_irq(M32R_IRQ_SIO1_R);



	/* SIO1_S : uart send data */

	irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_SIO1_S].action = 0;

	irq_desc[M32R_IRQ_SIO1_S].depth = 1;

	set_irq_chip(M32R_IRQ_SIO1_S, &mappi2_irq_type);

	icu_data[M32R_IRQ_SIO1_S].icucr = 0;

	disable_mappi2_irq(M32R_IRQ_SIO1_S);

#endif  /* CONFIG_M32R_USE_DBG_CONSOLE */



#if defined(CONFIG_USB)

	/* INT1 : USB Host controller interrupt */

	irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;

	irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;

	irq_desc[M32R_IRQ_INT1].action = 0;

	irq_desc[M32R_IRQ_INT1].depth = 1;

	set_irq_chip(M32R_IRQ_INT1, &mappi2_irq_type);

	icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;

	disable_mappi2_irq(M32R_IRQ_INT1);

#endif /* CONFIG_USB */



	/* ICUCR40: CFC IREQ */

	irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type;

	irq_desc[PLD_IRQ_CFIREQ].action = 0;

	irq_desc[PLD_IRQ_CFIREQ].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFIREQ, &mappi2_irq_type);

	icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;

	disable_mappi2_irq(PLD_IRQ_CFIREQ);



#if defined(CONFIG_M32R_CFC)

	/* ICUCR41: CFC Insert */

	irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type;

	irq_desc[PLD_IRQ_CFC_INSERT].action = 0;

	irq_desc[PLD_IRQ_CFC_INSERT].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFC_INSERT, &mappi2_irq_type);

	icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;

	disable_mappi2_irq(PLD_IRQ_CFC_INSERT);



	/* ICUCR42: CFC Eject */

	irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED;

	irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type;

	irq_desc[PLD_IRQ_CFC_EJECT].action = 0;

	irq_desc[PLD_IRQ_CFC_EJECT].depth = 1;	/* disable nested irq */

	set_irq_chip(PLD_IRQ_CFC_EJECT, &mappi2_irq_type);

	icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;

	disable_mappi2_irq(PLD_IRQ_CFC_EJECT);

#endif /* CONFIG_MAPPI2_CFC */