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Commit 8576f815 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
Browse files

ssb: move ssb_commit_settings and export it 



Commiting settings is possible on devices without PCI core (but with CC
core). Export it for usage in drivers supporting other cores.

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 1073e4ee

drivers/ssb/driver_pcicore.c

+0 −26
Original line number Diff line number Diff line
@@ -21,8 +21,6 @@ static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); 
static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,

				u8 address, u16 data);



static void ssb_commit_settings(struct ssb_bus *bus);



static inline

u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)

{
@@ -659,30 +657,6 @@ static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 
	pcicore_write32(pc, mdio_control, 0);

}



static void ssb_broadcast_value(struct ssb_device *dev,

				u32 address, u32 data)

{

	/* This is used for both, PCI and ChipCommon core, so be careful. */

	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);

	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);



	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);

	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */

	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);

	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */

}



static void ssb_commit_settings(struct ssb_bus *bus)

{

	struct ssb_device *dev;



	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;

	if (WARN_ON(!dev))

		return;

	/* This forces an update of the cached registers. */

	ssb_broadcast_value(dev, 0xFD8, 0);

}



int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,

				   struct ssb_device *dev)

{

drivers/ssb/main.c

+25 −0
Original line number Diff line number Diff line
@@ -1329,6 +1329,31 @@ int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) 
}

EXPORT_SYMBOL(ssb_bus_powerup);



static void ssb_broadcast_value(struct ssb_device *dev,

				u32 address, u32 data)

{

	/* This is used for both, PCI and ChipCommon core, so be careful. */

	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);

	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);



	ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);

	ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */

	ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);

	ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */

}



void ssb_commit_settings(struct ssb_bus *bus)

{

	struct ssb_device *dev;



	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;

	if (WARN_ON(!dev))

		return;

	/* This forces an update of the cached registers. */

	ssb_broadcast_value(dev, 0xFD8, 0);

}

EXPORT_SYMBOL(ssb_commit_settings);



u32 ssb_admatch_base(u32 adm)

{

	u32 base = 0;

include/linux/ssb/ssb.h

+1 −0
Original line number Diff line number Diff line
@@ -518,6 +518,7 @@ extern int ssb_bus_may_powerdown(struct ssb_bus *bus); 
 * Otherwise static always-on powercontrol will be used. */

extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);



extern void ssb_commit_settings(struct ssb_bus *bus);



/* Various helper functions */

extern u32 ssb_admatch_base(u32 adm);