Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 843fc75a authored by Thor Thayer's avatar Thor Thayer Committed by Philipp Zabel
Browse files

dt-bindings: reset: a10sr: Add Arria10 SR Reset Controller offsets 



The Arria10 System Resource Chip reset controller handles the
Arria10 peripheral PHYs. This patch adds the offsets for
these PHYs.

Signed-off-by: default avatarThor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent abf97755

MAINTAINERS

+1 −0
Original line number Original line Diff line number Diff line
@@ -654,6 +654,7 @@ S: Maintained 
F:	drivers/gpio/gpio-altera-a10sr.c

F:	drivers/gpio/gpio-altera-a10sr.c

F:	drivers/mfd/altera-a10sr.c

F:	drivers/mfd/altera-a10sr.c

F:	include/linux/mfd/altera-a10sr.h

F:	include/linux/mfd/altera-a10sr.h

F:	include/dt-bindings/reset/altr,rst-mgr-a10sr.h





ALTERA TRIPLE SPEED ETHERNET DRIVER

ALTERA TRIPLE SPEED ETHERNET DRIVER

M:	Vince Bridgers <vbridger@opensource.altera.com>

M:	Vince Bridgers <vbridger@opensource.altera.com>

include/dt-bindings/reset/altr,rst-mgr-a10sr.h

0 → 100644
+33 −0
Original line number Original line Diff line number Diff line 
/*

 *  Copyright Intel Corporation (C) 2017. All Rights Reserved

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License along with

 * this program.  If not, see <http://www.gnu.org/licenses/>.

 *

 * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip

 *

 * Adapted from altr,rst-mgr-a10.h

 */



#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H

#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10SR_H



/* Peripheral PHY resets */

#define A10SR_RESET_ENET_HPS	0

#define A10SR_RESET_PCIE	1

#define A10SR_RESET_FILE	2

#define A10SR_RESET_BQSPI	3

#define A10SR_RESET_USB		4



#define A10SR_RESET_NUM		5



#endif