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Commit 842ec8b6 authored by Bruce Allan's avatar Bruce Allan Committed by David S. Miller
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e1000e: read of PHY register may access wrong page on 82578 



Remove unnecessary workaround that mistakenly does not perform a page
select operation for PHY registers 29 and 30 (assuming these are the PHY
debug port address and data registers) on 82578 which can cause reads
of the Transmit with No Carrier Sense statistics register on page 778 to be
read from an incorrect page.  Also error out if the page select operation
fails.

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 38eb394e

drivers/net/e1000e/phy.c

+22 −24
Original line number Diff line number Diff line
@@ -2658,9 +2658,6 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 
		page = 0;



	if (reg > MAX_PHY_MULTI_PAGE_REG) {

		if ((hw->phy.type != e1000_phy_82578) ||

		    ((reg != I82578_ADDR_REG) &&

		     (reg != I82578_ADDR_REG + 1))) {

		u32 phy_addr = hw->phy.addr;



		hw->phy.addr = 1;
@@ -2670,7 +2667,9 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 
					     IGP01E1000_PHY_PAGE_SELECT,

					     (page << IGP_PAGE_SHIFT));

		hw->phy.addr = phy_addr;

		}



		if (ret_val)

			goto out;

	}



	ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2678,7 +2677,7 @@ static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 
out:

	/* Revert to MDIO fast mode, if applicable */

	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)

		ret_val = e1000_set_mdio_slow_mode_hv(hw, false);

		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);



	if (!locked)

		hw->phy.ops.release_phy(hw);
@@ -2784,9 +2783,6 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 
	}



	if (reg > MAX_PHY_MULTI_PAGE_REG) {

		if ((hw->phy.type != e1000_phy_82578) ||

		    ((reg != I82578_ADDR_REG) &&

		     (reg != I82578_ADDR_REG + 1))) {

		u32 phy_addr = hw->phy.addr;



		hw->phy.addr = 1;
@@ -2796,7 +2792,9 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 
					     IGP01E1000_PHY_PAGE_SELECT,

					     (page << IGP_PAGE_SHIFT));

		hw->phy.addr = phy_addr;

		}



		if (ret_val)

			goto out;

	}



	ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
@@ -2805,7 +2803,7 @@ static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 
out:

	/* Revert to MDIO fast mode, if applicable */

	if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)

		ret_val = e1000_set_mdio_slow_mode_hv(hw, false);

		ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);



	if (!locked)

		hw->phy.ops.release_phy(hw);