Loading arch/arm/boot/dts/imx51.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -409,6 +409,24 @@ }; }; pwm1: pwm@73fb4000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks 37>, <&clks 38>; clock-names = "ipg", "per"; interrupts = <61>; }; pwm2: pwm@73fb8000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks 39>, <&clks 40>; clock-names = "ipg", "per"; interrupts = <94>; }; uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; Loading Loading
arch/arm/boot/dts/imx51.dtsi +18 −0 Original line number Diff line number Diff line Loading @@ -409,6 +409,24 @@ }; }; pwm1: pwm@73fb4000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb4000 0x4000>; clocks = <&clks 37>, <&clks 38>; clock-names = "ipg", "per"; interrupts = <61>; }; pwm2: pwm@73fb8000 { #pwm-cells = <2>; compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; reg = <0x73fb8000 0x4000>; clocks = <&clks 39>, <&clks 40>; clock-names = "ipg", "per"; interrupts = <94>; }; uart1: serial@73fbc000 { compatible = "fsl,imx51-uart", "fsl,imx21-uart"; reg = <0x73fbc000 0x4000>; Loading