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Commit 825637b9 authored by Hai Li's avatar Hai Li Committed by Rob Clark
Browse files

drm/msm/dsi: Add DSI PLL clock driver support 



DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.

This change handles DSI 28nm PLL only.

Signed-off-by: default avatarHai Li <hali@codeaurora.org>
Signed-off-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarStephane Viau <sviau@codeaurora.org>
Signed-off-by: default avatarWentao Xu <wentaox@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent bdc80de2

drivers/gpu/drm/msm/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -46,3 +46,10 @@ config DRM_MSM_DSI 
	  Choose this option if you have a need for MIPI DSI connector

	  support.



config DRM_MSM_DSI_PLL

	bool "Enable DSI PLL driver in MSM DRM"

	depends on DRM_MSM_DSI && COMMON_CLK

	default y

	help

	  Choose this option to enable DSI PLL driver which provides DSI

	  source clocks under common clock framework.

drivers/gpu/drm/msm/Makefile

+5 −0
Original line number Diff line number Diff line 
ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm

ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi



msm-y := \

	adreno/adreno_device.o \
@@ -50,10 +51,14 @@ msm-y := \ 


msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o

msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o



msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \

			dsi/dsi_host.o \

			dsi/dsi_manager.o \

			dsi/dsi_phy.o \

			mdp/mdp5/mdp5_cmd_encoder.o



msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \

				dsi/pll/dsi_pll_28nm.o



obj-$(CONFIG_DRM_MSM)	+= msm.o

drivers/gpu/drm/msm/dsi/dsi.h

+2 −1
Original line number Diff line number Diff line
@@ -103,7 +103,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); 
struct msm_dsi_phy;

enum msm_dsi_phy_type {

	MSM_DSI_PHY_UNKNOWN,

	MSM_DSI_PHY_28NM,

	MSM_DSI_PHY_28NM_HPM,

	MSM_DSI_PHY_28NM_LP,

	MSM_DSI_PHY_MAX

};

struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,

drivers/gpu/drm/msm/dsi/dsi_host.c

+5 −5
Original line number Diff line number Diff line
@@ -64,7 +64,7 @@ static const struct dsi_config dsi_cfgs[] = { 
		.major = MSM_DSI_VER_MAJOR_6G,

		.minor = MSM_DSI_6G_VER_MINOR_V1_0,

		.io_offset = DSI_6G_REG_SHIFT,

		.phy_type = MSM_DSI_PHY_28NM,

		.phy_type = MSM_DSI_PHY_28NM_HPM,

		.reg_cfg = {

			.num = 4,

			.regs = {
@@ -79,7 +79,7 @@ static const struct dsi_config dsi_cfgs[] = { 
		.major = MSM_DSI_VER_MAJOR_6G,

		.minor = MSM_DSI_6G_VER_MINOR_V1_1,

		.io_offset = DSI_6G_REG_SHIFT,

		.phy_type = MSM_DSI_PHY_28NM,

		.phy_type = MSM_DSI_PHY_28NM_HPM,

		.reg_cfg = {

			.num = 4,

			.regs = {
@@ -94,7 +94,7 @@ static const struct dsi_config dsi_cfgs[] = { 
		.major = MSM_DSI_VER_MAJOR_6G,

		.minor = MSM_DSI_6G_VER_MINOR_V1_1_1,

		.io_offset = DSI_6G_REG_SHIFT,

		.phy_type = MSM_DSI_PHY_28NM,

		.phy_type = MSM_DSI_PHY_28NM_HPM,

		.reg_cfg = {

			.num = 4,

			.regs = {
@@ -109,7 +109,7 @@ static const struct dsi_config dsi_cfgs[] = { 
		.major = MSM_DSI_VER_MAJOR_6G,

		.minor = MSM_DSI_6G_VER_MINOR_V1_2,

		.io_offset = DSI_6G_REG_SHIFT,

		.phy_type = MSM_DSI_PHY_28NM,

		.phy_type = MSM_DSI_PHY_28NM_HPM,

		.reg_cfg = {

			.num = 4,

			.regs = {
@@ -124,7 +124,7 @@ static const struct dsi_config dsi_cfgs[] = { 
		.major = MSM_DSI_VER_MAJOR_6G,

		.minor = MSM_DSI_6G_VER_MINOR_V1_3_1,

		.io_offset = DSI_6G_REG_SHIFT,

		.phy_type = MSM_DSI_PHY_28NM,

		.phy_type = MSM_DSI_PHY_28NM_LP,

		.reg_cfg = {

			.num = 4,

			.regs = {

drivers/gpu/drm/msm/dsi/dsi_phy.c

+2 −1
Original line number Diff line number Diff line
@@ -311,7 +311,8 @@ struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev, 
	}



	switch (type) {

	case MSM_DSI_PHY_28NM:

	case MSM_DSI_PHY_28NM_HPM:

	case MSM_DSI_PHY_28NM_LP:

		dsi_phy_func_init(28nm);

		break;

	default: