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Commit 81fad217 authored by Paul Gortmaker's avatar Paul Gortmaker Committed by Kumar Gala
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[POWERPC] 86xx: Add device tree source for Wind River SBC8641D 



This adds in the device tree source for the SBC8641D, based
largely on the mpc8641_hpcn.dts.  The biggest differences are
the lack of a complex IRQ mapping (since no Uli/i8259 cascade)
and the different layout of devices on the localbus node.

Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 1c37dca5

arch/powerpc/boot/dts/sbc8641d.dts

0 → 100644
+352 −0
Original line number Diff line number Diff line 
/*

 * SBC8641D Device Tree Source

 *

 * Copyright 2008 Wind River Systems Inc.

 *

 * Paul Gortmaker (see MAINTAINERS for contact information)

 *

 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



/dts-v1/;



/ {

	model = "SBC8641D";

	compatible = "wind,sbc8641";

	#address-cells = <1>;

	#size-cells = <1>;



	aliases {

		ethernet0 = &enet0;

		ethernet1 = &enet1;

		ethernet2 = &enet2;

		ethernet3 = &enet3;

		serial0 = &serial0;

		serial1 = &serial1;

		pci0 = &pci0;

		pci1 = &pci1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,8641@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <32>;

			i-cache-line-size = <32>;

			d-cache-size = <32768>;		// L1

			i-cache-size = <32768>;		// L1

			timebase-frequency = <0>;	// From uboot

			bus-frequency = <0>;		// From uboot

			clock-frequency = <0>;		// From uboot

		};

		PowerPC,8641@1 {

			device_type = "cpu";

			reg = <1>;

			d-cache-line-size = <32>;

			i-cache-line-size = <32>;

			d-cache-size = <32768>;

			i-cache-size = <32768>;

			timebase-frequency = <0>;	// From uboot

			bus-frequency = <0>;		// From uboot

			clock-frequency = <0>;		// From uboot

		};

	};



	memory {

		device_type = "memory";

		reg = <0x00000000 0x20000000>;	// 512M at 0x0

	};



	localbus@f8005000 {

		#address-cells = <2>;

		#size-cells = <1>;

		compatible = "fsl,mpc8641-localbus", "simple-bus";

		reg = <0xf8005000 0x1000>;

		interrupts = <19 2>;

		interrupt-parent = <&mpic>;



		ranges = <0 0 0xff000000 0x01000000	// 16MB Boot flash

			  1 0 0xf0000000 0x00010000	// 64KB EEPROM

			  2 0 0xf1000000 0x00100000	// EPLD (1MB)

			  3 0 0xe0000000 0x04000000	// 64MB LB SDRAM (CS3)

			  4 0 0xe4000000 0x04000000	// 64MB LB SDRAM (CS4)

			  6 0 0xf4000000 0x00100000	// LCD display (1MB)

			  7 0 0xe8000000 0x04000000>;	// 64MB OneNAND



		flash@0,0 {

			compatible = "cfi-flash";

			reg = <0 0 0x01000000>;

			bank-width = <2>;

			device-width = <2>;

			#address-cells = <1>;

			#size-cells = <1>;

			partition@0 {

				label = "dtb";

				reg = <0x00000000 0x00100000>;

				read-only;

			};

			partition@300000 {

				label = "kernel";

				reg = <0x00100000 0x00400000>;

				read-only;

			};

			partition@400000 {

				label = "fs";

				reg = <0x00500000 0x00a00000>;

			};

			partition@700000 {

				label = "firmware";

				reg = <0x00f00000 0x00100000>;

				read-only;

			};

		};



		epld@2,0 {

			compatible = "wrs,epld-localbus";

			#address-cells = <2>;

			#size-cells = <1>;

			reg = <2 0 0x100000>;

			ranges = <0 0 5 0 1	// User switches

				  1 0 5 1 1	// Board ID/Rev

				  3 0 5 3 1>;	// LEDs

		};

	};



	soc@f8000000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		compatible = "simple-bus";

		ranges = <0x00000000 0xf8000000 0x00100000>;

		reg = <0xf8000000 0x00001000>;	// CCSRBAR

		bus-frequency = <0>;



		i2c@3000 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		i2c@3100 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <1>;

			compatible = "fsl-i2c";

			reg = <0x3100 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		mdio@24520 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,gianfar-mdio";

			reg = <0x24520 0x20>;



			phy0: ethernet-phy@1f {

				interrupt-parent = <&mpic>;

				interrupts = <10 1>;

				reg = <0x1f>;

				device_type = "ethernet-phy";

			};

			phy1: ethernet-phy@0 {

				interrupt-parent = <&mpic>;

				interrupts = <10 1>;

				reg = <0>;

				device_type = "ethernet-phy";

			};

			phy2: ethernet-phy@1 {

				interrupt-parent = <&mpic>;

				interrupts = <10 1>;

				reg = <1>;

				device_type = "ethernet-phy";

			};

			phy3: ethernet-phy@2 {

				interrupt-parent = <&mpic>;

				interrupts = <10 1>;

				reg = <2>;

				device_type = "ethernet-phy";

			};

		};



		enet0: ethernet@24000 {

			cell-index = <0>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x24000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <29 2 30  2 34 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy0>;

			phy-connection-type = "rgmii-id";

		};



		enet1: ethernet@25000 {

			cell-index = <1>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x25000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <35 2 36 2 40 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy1>;

			phy-connection-type = "rgmii-id";

		};



		enet2: ethernet@26000 {

			cell-index = <2>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x26000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <31 2 32 2 33 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy2>;

			phy-connection-type = "rgmii-id";

		};



		enet3: ethernet@27000 {

			cell-index = <3>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x27000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <37 2 38 2 39 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy3>;

			phy-connection-type = "rgmii-id";

		};



		serial0: serial@4500 {

			cell-index = <0>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};



		serial1: serial@4600 {

			cell-index = <1>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <28 2>;

			interrupt-parent = <&mpic>;

		};



		mpic: pic@40000 {

			clock-frequency = <0>;

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

			big-endian;

		};



		global-utilities@e0000 {

			compatible = "fsl,mpc8641-guts";

			reg = <0xe0000 0x1000>;

			fsl,has-rstcr;

		};

	};



	pci0: pcie@f8008000 {

		cell-index = <0>;

		compatible = "fsl,mpc8641-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xf8008000 0x1000>;

		bus-range = <0x0 0xff>;

		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000

			  0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;

		clock-frequency = <33333333>;

		interrupt-parent = <&mpic>;

		interrupts = <24 2>;

		interrupt-map-mask = <0xff00 0 0 7>;

		interrupt-map = <

			/* IDSEL 0x0 */

			0x0000 0 0 1 &mpic 0 1

			0x0000 0 0 2 &mpic 1 1

			0x0000 0 0 3 &mpic 2 1

			0x0000 0 0 4 &mpic 3 1

			>;



		pcie@0 {

			reg = <0 0 0 0 0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <0x02000000 0x0 0x80000000

				  0x02000000 0x0 0x80000000

				  0x0 0x20000000



				  0x01000000 0x0 0x00000000

				  0x01000000 0x0 0x00000000

				  0x0 0x00100000>;

		};



	};



	pci1: pcie@f8009000 {

		cell-index = <1>;

		compatible = "fsl,mpc8641-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xf8009000 0x1000>;

		bus-range = <0 0xff>;

		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000

			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;

		clock-frequency = <33333333>;

		interrupt-parent = <&mpic>;

		interrupts = <25 2>;

		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <

			/* IDSEL 0x0 */

			0x0000 0 0 1 &mpic 4 1

			0x0000 0 0 2 &mpic 5 1

			0x0000 0 0 3 &mpic 6 1

			0x0000 0 0 4 &mpic 7 1

			>;



		pcie@0 {

			reg = <0 0 0 0 0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <0x02000000 0x0 0xa0000000

				  0x02000000 0x0 0xa0000000

				  0x0 0x20000000



				  0x01000000 0x0 0x00000000

				  0x01000000 0x0 0x00000000

				  0x0 0x00100000>;

		};

	};

};