Loading arch/x86/Kconfig.cpu +18 −0 Original line number Diff line number Diff line Loading @@ -477,3 +477,21 @@ config CPU_SUP_UMC_32 depends on !64BIT help This enables extended support for UMC processors config X86_DS bool "Debug Store support" default y help Add support for Debug Store. This allows the kernel to provide a memory buffer to the hardware to store various profiling and tracing events. config X86_PTRACE_BTS bool "ptrace interface to Branch Trace Store" default y depends on (X86_DS && X86_DEBUGCTLMSR) help Add a ptrace interface to allow collecting an execution trace of the traced task. This collects control flow changes in a (cyclic) buffer and allows debuggers to fill in the gaps and show an execution trace of the debuggee. arch/x86/kernel/cpu/intel.c +2 −1 Original line number Diff line number Diff line Loading @@ -221,10 +221,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_BTS); if (!(l1 & (1<<12))) set_cpu_cap(c, X86_FEATURE_PEBS); ds_init_intel(c); } if (cpu_has_bts) ds_init_intel(c); ptrace_bts_init_intel(c); /* * See if we have a good local APIC by checking for buggy Pentia, Loading Loading
arch/x86/Kconfig.cpu +18 −0 Original line number Diff line number Diff line Loading @@ -477,3 +477,21 @@ config CPU_SUP_UMC_32 depends on !64BIT help This enables extended support for UMC processors config X86_DS bool "Debug Store support" default y help Add support for Debug Store. This allows the kernel to provide a memory buffer to the hardware to store various profiling and tracing events. config X86_PTRACE_BTS bool "ptrace interface to Branch Trace Store" default y depends on (X86_DS && X86_DEBUGCTLMSR) help Add a ptrace interface to allow collecting an execution trace of the traced task. This collects control flow changes in a (cyclic) buffer and allows debuggers to fill in the gaps and show an execution trace of the debuggee.
arch/x86/kernel/cpu/intel.c +2 −1 Original line number Diff line number Diff line Loading @@ -221,10 +221,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_BTS); if (!(l1 & (1<<12))) set_cpu_cap(c, X86_FEATURE_PEBS); ds_init_intel(c); } if (cpu_has_bts) ds_init_intel(c); ptrace_bts_init_intel(c); /* * See if we have a good local APIC by checking for buggy Pentia, Loading