Loading Documentation/admin-guide/kernel-parameters.txt +7 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,13 @@ irqaffinity= [SMP] Set the default irq affinity mask The argument is a cpu list, as described above. irqchip.gicv2_force_probe= [ARM, ARM64] Format: <bool> Force the kernel to look for the second 4kB page of a GICv2 controller even if the memory range exposed by the device tree is too small. irqfixup [HW] When an interrupt is not handled search all handlers for it. Intended to get systems with badly broken Loading Documentation/arm64/silicon-errata.txt +1 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | | Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | Loading Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt 0 → 100644 +36 −0 Original line number Diff line number Diff line Amlogic meson GPIO interrupt controller Meson SoCs contains an interrupt controller which is able to watch the SoC pads and generate an interrupt on edge or level. The controller is essentially a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge or level and polarity. It does not expose all 256 mux inputs because the documentation shows that the upper part is not mapped to any pad. The actual number of interrupt exposed depends on the SoC. Required properties: - compatible : must have "amlogic,meson8-gpio-intc” and either “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912) - interrupt-parent : a phandle to the GIC the interrupts are routed to. Usually this is provided at the root level of the device tree as it is common to most of the SoC. - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value must be 2. - meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These are the hwirqs used on the parent interrupt controller. Example: gpio_interrupt: interrupt-controller@9880 { compatible = "amlogic,meson-gxbb-gpio-intc", "amlogic,meson-gpio-intc"; reg = <0x0 0x9880 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; meson,channel-interrupts = <64 65 66 67 68 69 70 71>; }; Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +4 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. Optional: - socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated address and size of the pre-ITS window. The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. Loading Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt +2 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller Required properties: - compatible: should be "brcm,l2-intc" - compatible: should be "brcm,l2-intc" for latched interrupt controllers should be "brcm,bcm7271-l2-intc" for level interrupt controllers - reg: specifies the base physical address and size of the registers - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an Loading Loading
Documentation/admin-guide/kernel-parameters.txt +7 −0 Original line number Diff line number Diff line Loading @@ -1713,6 +1713,13 @@ irqaffinity= [SMP] Set the default irq affinity mask The argument is a cpu list, as described above. irqchip.gicv2_force_probe= [ARM, ARM64] Format: <bool> Force the kernel to look for the second 4kB page of a GICv2 controller even if the memory range exposed by the device tree is too small. irqfixup [HW] When an interrupt is not handled search all handlers for it. Intended to get systems with badly broken Loading
Documentation/arm64/silicon-errata.txt +1 −0 Original line number Diff line number Diff line Loading @@ -70,6 +70,7 @@ stable kernels. | | | | | | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | | Hisilicon | Hip0{6,7} | #161010701 | N/A | | Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 | | | | | | | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 | Loading
Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt 0 → 100644 +36 −0 Original line number Diff line number Diff line Amlogic meson GPIO interrupt controller Meson SoCs contains an interrupt controller which is able to watch the SoC pads and generate an interrupt on edge or level. The controller is essentially a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge or level and polarity. It does not expose all 256 mux inputs because the documentation shows that the upper part is not mapped to any pad. The actual number of interrupt exposed depends on the SoC. Required properties: - compatible : must have "amlogic,meson8-gpio-intc” and either “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912) - interrupt-parent : a phandle to the GIC the interrupts are routed to. Usually this is provided at the root level of the device tree as it is common to most of the SoC. - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an interrupt source. The value must be 2. - meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These are the hwirqs used on the parent interrupt controller. Example: gpio_interrupt: interrupt-controller@9880 { compatible = "amlogic,meson-gxbb-gpio-intc", "amlogic,meson-gpio-intc"; reg = <0x0 0x9880 0x0 0x10>; interrupt-controller; #interrupt-cells = <2>; meson,channel-interrupts = <64 65 66 67 68 69 70 71>; };
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +4 −0 Original line number Diff line number Diff line Loading @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. Optional: - socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated address and size of the pre-ITS window. The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. Loading
Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt +2 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,8 @@ Broadcom Generic Level 2 Interrupt Controller Required properties: - compatible: should be "brcm,l2-intc" - compatible: should be "brcm,l2-intc" for latched interrupt controllers should be "brcm,bcm7271-l2-intc" for level interrupt controllers - reg: specifies the base physical address and size of the registers - interrupt-controller: identifies the node as an interrupt controller - #interrupt-cells: specifies the number of cells needed to encode an Loading
