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Commit 8097d4c7 authored by Thierry Reding's avatar Thierry Reding Committed by Stephen Boyd
Browse files

clk: tegra: Make vde a child of pll_c3 



The current default is to leave the VDE clock's parent at the default,
which is clk_m. However, that is not a configuration that will allow the
VDE to function. Reparent it to pll_c3 instead to make sure the hardware
can actually decode video content.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 26f8590c

drivers/clk/tegra/clk-tegra124.c

+1 −1
Original line number Diff line number Diff line
@@ -1267,7 +1267,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = { 
	{ TEGRA124_CLK_I2S2, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },

	{ TEGRA124_CLK_I2S3, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },

	{ TEGRA124_CLK_I2S4, TEGRA124_CLK_PLL_A_OUT0, 11289600, 0 },

	{ TEGRA124_CLK_VDE, TEGRA124_CLK_CLK_MAX, 600000000, 0 },

	{ TEGRA124_CLK_VDE, TEGRA124_CLK_PLL_C3, 600000000, 0 },

	{ TEGRA124_CLK_HOST1X, TEGRA124_CLK_PLL_P, 136000000, 1 },

	{ TEGRA124_CLK_DSIALP, TEGRA124_CLK_PLL_P, 68000000, 0 },

	{ TEGRA124_CLK_DSIBLP, TEGRA124_CLK_PLL_P, 68000000, 0 },