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Commit 80130204 authored by Manuel Lauss's avatar Manuel Lauss Committed by Ralf Baechle
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MIPS: Alchemy: Rewrite UART setup and constants. 



Detect CPU type at runtime and setup uarts accordingly; also clean up the
uart base address mess in the process as far as possible.

Signed-off-by: default avatarManuel Lauss <manuel.lauss@googlemail.com>
To: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Florian Fainelli <florian@openwrt.org>
Cc: Wolfgang Grandegger <wg@grandegger.com>
Patchwork: https://patchwork.linux-mips.org/patch/2352/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent adcb8627

arch/mips/alchemy/common/platform.c

+51 −42
Original line number Diff line number Diff line
@@ -30,21 +30,12 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 
#ifdef CONFIG_SERIAL_8250

	switch (state) {

	case 0:

		if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) {

			/* power-on sequence as suggested in the databooks */

			__raw_writel(0, port->membase + UART_MOD_CNTRL);

			wmb();

			__raw_writel(1, port->membase + UART_MOD_CNTRL);

			wmb();

		}

		__raw_writel(3, port->membase + UART_MOD_CNTRL); /* full on */

		wmb();

		alchemy_uart_enable(CPHYSADDR(port->membase));

		serial8250_do_pm(port, state, old_state);

		break;

	case 3:		/* power off */

		serial8250_do_pm(port, state, old_state);

		__raw_writel(0, port->membase + UART_MOD_CNTRL);

		wmb();

		alchemy_uart_disable(CPHYSADDR(port->membase));

		break;

	default:

		serial8250_do_pm(port, state, old_state);
@@ -65,38 +56,60 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state, 
		.pm		= alchemy_8250_pm,		\

	}



static struct plat_serial8250_port au1x00_uart_data[] = {

#if defined(CONFIG_SOC_AU1000)

	PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),

	PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),

	PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),

	PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),

#elif defined(CONFIG_SOC_AU1500)

	PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),

	PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),

#elif defined(CONFIG_SOC_AU1100)

	PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),

	PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),

	PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),

#elif defined(CONFIG_SOC_AU1550)

	PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),

	PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),

	PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),

#elif defined(CONFIG_SOC_AU1200)

	PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),

	PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),

#endif

	{ },

static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {

	[ALCHEMY_CPU_AU1000] = {

		PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),

		PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),

		PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),

		PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),

	},

	[ALCHEMY_CPU_AU1500] = {

		PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),

		PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),

	},

	[ALCHEMY_CPU_AU1100] = {

		PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),

		PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),

		PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),

	},

	[ALCHEMY_CPU_AU1550] = {

		PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),

		PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),

		PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),

	},

	[ALCHEMY_CPU_AU1200] = {

		PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),

		PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),

	},

};



static struct platform_device au1xx0_uart_device = {

	.name			= "serial8250",

	.id			= PLAT8250_DEV_AU1X00,

	.dev			= {

		.platform_data	= au1x00_uart_data,

	},

};



static void __init alchemy_setup_uarts(int ctype)

{

	unsigned int uartclk = get_au1x00_uart_baud_base() * 16;

	int s = sizeof(struct plat_serial8250_port);

	int c = alchemy_get_uarts(ctype);

	struct plat_serial8250_port *ports;



	ports = kzalloc(s * (c + 1), GFP_KERNEL);

	if (!ports) {

		printk(KERN_INFO "Alchemy: no memory for UART data\n");

		return;

	}

	memcpy(ports, au1x00_uart_data[ctype], s * c);

	au1xx0_uart_device.dev.platform_data = ports;



	/* Fill up uartclk. */

	for (s = 0; s < c; s++)

		ports[s].uartclk = uartclk;

	if (platform_device_register(&au1xx0_uart_device))

		printk(KERN_INFO "Alchemy: failed to register UARTs\n");

}



/* OHCI (USB full speed host controller) */

static struct resource au1xxx_usb_ohci_resources[] = {

	[0] = {
@@ -442,7 +455,6 @@ void __init au1xxx_override_eth_cfg(unsigned int port, 
}



static struct platform_device *au1xxx_platform_devices[] __initdata = {

	&au1xx0_uart_device,

	&au1xxx_usb_ohci_device,

#ifdef CONFIG_FB_AU1100

	&au1100_lcd_device,
@@ -465,13 +477,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { 


static int __init au1xxx_platform_init(void)

{

	unsigned int uartclk = get_au1x00_uart_baud_base() * 16;

	int err, i;

	int err, i, ctype = alchemy_get_cputype();

	unsigned char ethaddr[6];



	/* Fill up uartclk. */

	for (i = 0; au1x00_uart_data[i].flags; i++)

		au1x00_uart_data[i].uartclk = uartclk;

	alchemy_setup_uarts(ctype);



	/* use firmware-provided mac addr if available and necessary */

	i = prom_get_ethernet_addr(ethaddr);

arch/mips/alchemy/devboards/prom.c

+1 −1
Original line number Diff line number Diff line
@@ -62,5 +62,5 @@ void __init prom_init(void) 


void prom_putchar(unsigned char c)

{

    alchemy_uart_putchar(UART0_PHYS_ADDR, c);

	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);

}

arch/mips/alchemy/gpr/board_setup.c

+4 −10
Original line number Diff line number Diff line
@@ -36,9 +36,6 @@ 


#include <prom.h>



#define UART1_ADDR	KSEG1ADDR(UART1_PHYS_ADDR)

#define UART3_ADDR	KSEG1ADDR(UART3_PHYS_ADDR)



char irq_tab_alchemy[][5] __initdata = {

	[0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },

};
@@ -67,18 +64,15 @@ static void gpr_power_off(void) 


void __init board_setup(void)

{

	printk(KERN_INFO "Tarpeze ITS GPR board\n");

	printk(KERN_INFO "Trapeze ITS GPR board\n");



	pm_power_off = gpr_power_off;

	_machine_halt = gpr_power_off;

	_machine_restart = gpr_reset;



	/* Enable UART3 */

	au_writel(0x1, UART3_ADDR + UART_MOD_CNTRL);/* clock enable (CE) */

	au_writel(0x3, UART3_ADDR + UART_MOD_CNTRL); /* CE and "enable" */

	/* Enable UART1 */

	au_writel(0x1, UART1_ADDR + UART_MOD_CNTRL); /* clock enable (CE) */

	au_writel(0x3, UART1_ADDR + UART_MOD_CNTRL); /* CE and "enable" */

	/* Enable UART1/3 */

	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);

	alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);



	/* Take away Reset of UMTS-card */

	alchemy_gpio_direction_output(215, 1);

arch/mips/alchemy/gpr/init.c

+1 −1
Original line number Diff line number Diff line
@@ -59,5 +59,5 @@ void __init prom_init(void) 


void prom_putchar(unsigned char c)

{

	alchemy_uart_putchar(UART0_PHYS_ADDR, c);

	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);

}

arch/mips/alchemy/mtx-1/init.c

+1 −1
Original line number Diff line number Diff line
@@ -62,5 +62,5 @@ void __init prom_init(void) 


void prom_putchar(unsigned char c)

{

	alchemy_uart_putchar(UART0_PHYS_ADDR, c);

	alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);

}