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Commit 801173fe authored by Jagan Teki's avatar Jagan Teki Committed by Shawn Guo
Browse files

ARM: dts: imx6qdl-icore: Add FEC support 

Add FEC support for Engicam i.CoreM6 dql modules.

Observed similar 'eth0: link is not ready' issue which was
discussed in [1] due rmii mode with external ref_clk, so added
clock node along with the properties mentioned by Shawn in [2]

FEC link log:
------------
$ ifconfig eth0 up
[   27.905187] SMSC LAN8710/LAN8720 2188000.ethernet:00: attached PHY driver
               [SMSC LAN8710/LAN8720] (mii_bus:phy_addr=2188000.ethernet:00, irq=-1)
[   27.918982] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready

[1] https://patchwork.kernel.org/patch/3491061/
[2] https://patchwork.kernel.org/patch/3490511/



Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9daee307

arch/arm/boot/dts/imx6qdl-icore.dtsi

+31 −0
Original line number Original line Diff line number Diff line
@@ -74,6 +74,12 @@ 
		regulator-boot-on;

		regulator-boot-on;

		regulator-always-on;

		regulator-always-on;

	};

	};



	rmii_clk: clock-rmii-clk {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <25000000>;  /* 25MHz for example */

	};

};

};





&can1 {

&can1 {
@@ -93,6 +99,15 @@ 
	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;

	assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>;

};

};





&fec {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_enet>;

	phy-reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;

	clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;

	phy-mode = "rmii";

	status = "okay";

};



&gpmi {

&gpmi {

	pinctrl-names = "default";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gpmi_nand>;

	pinctrl-0 = <&pinctrl_gpmi_nand>;
@@ -150,6 +165,22 @@ 
};

};





&iomuxc {

&iomuxc {

	pinctrl_enet: enetgrp {

		fsl,pins = <

			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0

			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x1b0b1

			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0

			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0

			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0

			MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0

			MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0

			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0

			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0

			MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23	0x1b0b0

			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x1b0b0

		>;

	};



	pinctrl_flexcan1: flexcan1grp {

	pinctrl_flexcan1: flexcan1grp {

		fsl,pins = <

		fsl,pins = <

			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020

			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b020