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Commit 7e772edf authored by Rob Herring's avatar Rob Herring Committed by Bjorn Helgaas
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PCI: versatile: Add DT docs for ARM Versatile PB PCIe driver 



Add binding documentation for the PCI controller found on Versatile PB
boards.

Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
parent 97bf6af1

Documentation/devicetree/bindings/pci/versatile.txt

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* ARM Versatile Platform Baseboard PCI interface



PCI host controller found on the ARM Versatile PB board's FPGA.



Required properties:

- compatible: should contain "arm,versatile-pci" to identify the Versatile PCI

  controller.

- reg: base addresses and lengths of the pci controller. There must be 3

  entries:

	- Versatile-specific registers

	- Self Config space

	- Config space

- #address-cells: set to <3>

- #size-cells: set to <2>

- device_type: set to "pci"

- bus-range: set to <0 0xff>

- ranges: ranges for the PCI memory and I/O regions

- #interrupt-cells: set to <1>

- interrupt-map-mask and interrupt-map: standard PCI properties to define

	the mapping of the PCI interface to interrupt numbers.



Example:



pci-controller@10001000 {

	compatible = "arm,versatile-pci";

	device_type = "pci";

	reg = <0x10001000 0x1000

	       0x41000000 0x10000

	       0x42000000 0x100000>;

	bus-range = <0 0xff>;

	#address-cells = <3>;

	#size-cells = <2>;

	#interrupt-cells = <1>;



	ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */

		  0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */

		  0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */



	interrupt-map-mask = <0x1800 0 0 7>;

	interrupt-map = <0x1800 0 0 1 &sic 28

			 0x1800 0 0 2 &sic 29

			 0x1800 0 0 3 &sic 30

			 0x1800 0 0 4 &sic 27



			 0x1000 0 0 1 &sic 27

			 0x1000 0 0 2 &sic 28

			 0x1000 0 0 3 &sic 29

			 0x1000 0 0 4 &sic 30



			 0x0800 0 0 1 &sic 30

			 0x0800 0 0 2 &sic 27

			 0x0800 0 0 3 &sic 28

			 0x0800 0 0 4 &sic 29



			 0x0000 0 0 1 &sic 29

			 0x0000 0 0 2 &sic 30

			 0x0000 0 0 3 &sic 27

			 0x0000 0 0 4 &sic 28>;

};