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Commit 7dae69a2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: fetch cu_info once at init 



Fetch this info once at init and just store the results
for future requests.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edf600da

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+9 −11
Original line number Diff line number Diff line
@@ -1148,6 +1148,12 @@ struct amdgpu_gca_config { 
	uint32_t macrotile_mode_array[16];

};



struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t bitmap[4][4];

};



struct amdgpu_gfx {

	struct mutex			gpu_clock_mutex;

	struct amdgpu_gca_config	config;
@@ -1183,6 +1189,7 @@ struct amdgpu_gfx { 
	uint32_t			gfx_current_status;

	/* ce ram size*/

	unsigned			ce_ram_size;

	struct amdgpu_cu_info		cu_info;

};



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1794,13 +1801,6 @@ struct amdgpu_allowed_register_entry { 
	bool grbm_indexed;

};



struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t bitmap[4][4];

};





/*

 * ASIC specific functions.

 */
@@ -1818,7 +1818,6 @@ struct amdgpu_asic_funcs { 
	u32 (*get_xclk)(struct amdgpu_device *adev);

	/* get the gpu clock counter */

	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);

	/* MM block clocks */

	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
@@ -2210,7 +2209,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+1 −3
Original line number Diff line number Diff line
@@ -793,7 +793,6 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 
				struct cgs_system_info *sys_info)

{

	CGS_FUNC_ADEV;

	struct amdgpu_cu_info cu_info;



	if (NULL == sys_info)

		return -ENODEV;
@@ -818,8 +817,7 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 
		sys_info->value = adev->pg_flags;

		break;

	case CGS_SYSTEM_INFO_GFX_CU_INFO:

		amdgpu_asic_get_cu_info(adev, &cu_info);

		sys_info->value = cu_info.number;

		sys_info->value = adev->gfx.cu_info.number;

		break;

	default:

		return -ENODEV;

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+4 −5
Original line number Diff line number Diff line
@@ -427,7 +427,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
	}

	case AMDGPU_INFO_DEV_INFO: {

		struct drm_amdgpu_info_device dev_info = {};

		struct amdgpu_cu_info cu_info;



		dev_info.device_id = dev->pdev->device;

		dev_info.chip_rev = adev->rev_id;
@@ -461,11 +460,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
					     AMDGPU_GPU_PAGE_SIZE;

		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;



		amdgpu_asic_get_cu_info(adev, &cu_info);

		dev_info.cu_active_number = cu_info.number;

		dev_info.cu_ao_mask = cu_info.ao_cu_mask;

		dev_info.cu_active_number = adev->gfx.cu_info.number;

		dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;

		dev_info.ce_ram_size = adev->gfx.ce_ram_size;

		memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap));

		memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],

		       sizeof(adev->gfx.cu_info.bitmap));

		dev_info.vram_type = adev->mc.vram_type;

		dev_info.vram_bit_width = adev->mc.vram_width;

		dev_info.vce_harvest_config = adev->vce.harvest_config;

drivers/gpu/drm/amd/amdgpu/cik.c

+0 −1
Original line number Diff line number Diff line
@@ -2007,7 +2007,6 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = 
	.get_xclk = &cik_get_xclk,

	.set_uvd_clocks = &cik_set_uvd_clocks,

	.set_vce_clocks = &cik_set_vce_clocks,

	.get_cu_info = &gfx_v7_0_get_cu_info,

	/* these should be moved to their own ip modules */

	.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,

	.wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+7 −16
Original line number Diff line number Diff line
@@ -53,7 +53,6 @@ 
static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);

static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);

static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);

int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);



MODULE_FIRMWARE("radeon/bonaire_pfp.bin");

MODULE_FIRMWARE("radeon/bonaire_me.bin");
@@ -882,6 +881,7 @@ static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev); 
static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);

static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);

static void gfx_v7_0_init_pg(struct amdgpu_device *adev);

static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev);



/*

 * Core functions
@@ -1718,6 +1718,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) 
	gfx_v7_0_tiling_mode_table_init(adev);



	gfx_v7_0_setup_rb(adev);

	gfx_v7_0_get_cu_info(adev);



	/* set HW defaults for 3D engine */

	WREG32(mmCP_MEQ_THRESHOLDS,
@@ -3869,18 +3870,13 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev) 


static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)

{

	uint32_t tmp, active_cu_number;

	struct amdgpu_cu_info cu_info;



	gfx_v7_0_get_cu_info(adev, &cu_info);

	tmp = cu_info.ao_cu_mask;

	active_cu_number = cu_info.number;

	u32 tmp;



	WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);

	WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);



	tmp = RREG32(mmRLC_MAX_PG_CU);

	tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;

	tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);

	tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);

	WREG32(mmRLC_MAX_PG_CU, tmp);

}
@@ -5015,14 +5011,11 @@ static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev) 
}





int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,

			 struct amdgpu_cu_info *cu_info)

static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)

{

	int i, j, k, counter, active_cu_number = 0;

	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;



	if (!adev || !cu_info)

		return -EINVAL;

	struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;



	memset(cu_info, 0, sizeof(*cu_info));
@@ -5053,6 +5046,4 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev, 


	cu_info->number = active_cu_number;

	cu_info->ao_cu_mask = ao_cu_mask;



	return 0;

}