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Commit 7d681b23 authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc32: Fix MPC83xx IPIC external interrupt pending register offset 



The pending registers for IRQ1-IRQ7 were pointing to the interrupt pending
register instead of the external one.

Signed-off-by: default avatarTony Li <Tony.Li@freescale.com>
Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 340ea397

arch/ppc/syslib/ipic.c

+7 −7
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 7,

	},

	[17] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SEFCR,
@@ -87,7 +87,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 5,

	},

	[18] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SEFCR,
@@ -95,7 +95,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 6,

	},

	[19] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SEFCR,
@@ -103,7 +103,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 7,

	},

	[20] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SEFCR,
@@ -111,7 +111,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 4,

	},

	[21] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SEFCR,
@@ -119,7 +119,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 5,

	},

	[22] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SEFCR,
@@ -127,7 +127,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 6,

	},

	[23] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SEPNR,

		.mask	= IPIC_SEMSR,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SEFCR,