Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7d020672 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux into drm-next 

More amdgpu fixes for 4.7.  Highlights:
- enable async pageflips
- UVD fixes for polaris
- lots of GPUVM fixes
- whitespace and code cleanups
- misc bug fixes

* 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux: (32 commits)
  drm/amd/powerplay: rewrite pp_sw_init to make code readable
  drm/amdgpu/dce11: fix audio offset for asics with >7 audio pins
  drm/amdgpu: fix and cleanup user fence handling v2
  drm/amdgpu: move VM fields into job
  drm/amdgpu: move the context from the IBs into the job
  drm/amdgpu: move context switch handling into common code v2
  drm/amdgpu: move preamble IB handling into common code
  drm/amdgpu/gfx7: fix pipeline sync
  amdgpu/uvd: separate context buffer from DPB
  drm/amdgpu: use fence_context to judge ctx switch v2
  drm/amd/amdgpu:  Added more named DRM info messages for debugging
  drm/amd/amdgpu: Add name field to amd_ip_funcs (v2)
  drm/amdgpu: Support DRM_MODE_PAGE_FLIP_ASYNC (v2)
  drm/amdgpu/dce11: don't share PLLs on Polaris
  drm/amdgpu: Drop unused parameter for *get_sleep_divider_id_from_clock
  drm/amdgpu: Simplify calculation in *get_sleep_divider_id_from_clock
  drm/amdgpu: Use max macro in *get_sleep_divider_id_from_clock
  drm/amd/powerplay: Use defined constants for minium engine clock
  drm/amdgpu: add missing licenses on a couple of files
  drm/amdgpu: fetch cu_info once at init
  ...
parents 95306975 b4eeed59

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+47 −45
Original line number Diff line number Diff line
@@ -283,7 +283,8 @@ struct amdgpu_ring_funcs { 
	int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);

	/* command emit functions */

	void (*emit_ib)(struct amdgpu_ring *ring,

			struct amdgpu_ib *ib);

			struct amdgpu_ib *ib,

			unsigned vm_id, bool ctx_switch);

	void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,

			   uint64_t seq, unsigned flags);

	void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
@@ -367,13 +368,6 @@ struct amdgpu_fence_driver { 
#define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)

#define AMDGPU_FENCE_FLAG_INT           (1 << 1)



struct amdgpu_user_fence {

	/* write-back bo */

	struct amdgpu_bo 	*bo;

	/* write-back address offset to bo start */

	uint32_t                offset;

};



int amdgpu_fence_driver_init(struct amdgpu_device *adev);

void amdgpu_fence_driver_fini(struct amdgpu_device *adev);

void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
@@ -507,7 +501,8 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, 
				struct drm_file *file_priv);

unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);

struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);

struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,

struct drm_gem_object *

amdgpu_gem_prime_import_sg_table(struct drm_device *dev,

				 struct dma_buf_attachment *attach,

				 struct sg_table *sg);

struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
@@ -726,6 +721,7 @@ struct amdgpu_flip_work { 
	unsigned			shared_count;

	struct fence			**shared;

	struct fence_cb			cb;

	bool				async;

};
@@ -738,17 +734,7 @@ struct amdgpu_ib { 
	uint32_t			length_dw;

	uint64_t			gpu_addr;

	uint32_t			*ptr;

	struct amdgpu_user_fence        *user;

	struct amdgpu_vm		*vm;

	unsigned			vm_id;

	uint64_t			vm_pd_addr;

	struct amdgpu_ctx		*ctx;

	uint32_t			gds_base, gds_size;

	uint32_t			gws_base, gws_size;

	uint32_t			oa_base, oa_size;

	uint32_t			flags;

	/* resulting sequence number */

	uint64_t			sequence;

};



enum amdgpu_ring_type {
@@ -762,7 +748,7 @@ enum amdgpu_ring_type { 
extern const struct amd_sched_backend_ops amdgpu_sched_ops;



int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job);

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

			     struct amdgpu_job **job);
@@ -805,7 +791,7 @@ struct amdgpu_ring { 
	unsigned		wptr_offs;

	unsigned		next_rptr_offs;

	unsigned		fence_offs;

	struct amdgpu_ctx	*current_ctx;

	uint64_t		current_ctx;

	enum amdgpu_ring_type	type;

	char			name[16];

	unsigned		cond_exe_offs;
@@ -885,6 +871,9 @@ struct amdgpu_vm { 


	/* Scheduler entity for page table updates */

	struct amd_sched_entity	entity;



	/* client id */

	u64                     client_id;

};



struct amdgpu_vm_id {
@@ -893,7 +882,7 @@ struct amdgpu_vm_id { 
	struct amdgpu_sync	active;

	struct fence		*last_flush;

	struct amdgpu_ring      *last_user;

	atomic_long_t		owner;

	atomic64_t		owner;



	uint64_t		pd_gpu_addr;

	/* last flushed PD/PT update */
@@ -924,6 +913,8 @@ struct amdgpu_vm_manager { 
	struct amdgpu_ring                      *vm_pte_rings[AMDGPU_MAX_RINGS];

	unsigned				vm_pte_num_rings;

	atomic_t				vm_pte_next_ring;

	/* client id counter */

	atomic64_t				client_counter;

};



void amdgpu_vm_manager_init(struct amdgpu_device *adev);
@@ -1143,6 +1134,12 @@ struct amdgpu_gca_config { 
	uint32_t macrotile_mode_array[16];

};



struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t bitmap[4][4];

};



struct amdgpu_gfx {

	struct mutex			gpu_clock_mutex;

	struct amdgpu_gca_config	config;
@@ -1178,14 +1175,16 @@ struct amdgpu_gfx { 
	uint32_t			gfx_current_status;

	/* ce ram size*/

	unsigned			ce_ram_size;

	struct amdgpu_cu_info		cu_info;

};



int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

		  unsigned size, struct amdgpu_ib *ib);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);

void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,

		    struct fence *f);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

		       struct amdgpu_ib *ib, struct fence *last_vm_update,

		       struct fence **f);

		       struct amdgpu_job *job, struct fence **f);

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
@@ -1210,7 +1209,7 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring); 
struct amdgpu_cs_chunk {

	uint32_t		chunk_id;

	uint32_t		length_dw;

	uint32_t		*kdata;

	void			*kdata;

};



struct amdgpu_cs_parser {
@@ -1241,13 +1240,25 @@ struct amdgpu_cs_parser { 
struct amdgpu_job {

	struct amd_sched_job    base;

	struct amdgpu_device	*adev;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	struct amdgpu_sync	sync;

	struct amdgpu_ib	*ibs;

	struct fence		*fence; /* the hw fence */

	uint32_t		num_ibs;

	void			*owner;

	struct amdgpu_user_fence uf;

	uint64_t		ctx;

	unsigned		vm_id;

	uint64_t		vm_pd_addr;

	uint32_t		gds_base, gds_size;

	uint32_t		gws_base, gws_size;

	uint32_t		oa_base, oa_size;



	/* user fence handling */

	struct amdgpu_bo	*uf_bo;

	uint32_t		uf_offset;

	uint64_t		uf_sequence;



};

#define to_amdgpu_job(sched_job)		\

		container_of((sched_job), struct amdgpu_job, base)
@@ -1787,13 +1798,6 @@ struct amdgpu_allowed_register_entry { 
	bool grbm_indexed;

};



struct amdgpu_cu_info {

	uint32_t number; /* total active CU number */

	uint32_t ao_cu_mask;

	uint32_t bitmap[4][4];

};





/*

 * ASIC specific functions.

 */
@@ -1811,7 +1815,6 @@ struct amdgpu_asic_funcs { 
	u32 (*get_xclk)(struct amdgpu_device *adev);

	/* get the gpu clock counter */

	uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

	int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);

	/* MM block clocks */

	int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

	int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
@@ -2203,7 +2206,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
@@ -2215,7 +2217,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))

#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))

#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))

#define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))

#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))

#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))

#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
@@ -2238,7 +2240,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 
#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))

#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))

#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))

#define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))

#define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))

#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))

#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))

#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+1 −0
Original line number Diff line number Diff line
@@ -480,6 +480,7 @@ static int acp_set_powergating_state(void *handle, 
}



const struct amd_ip_funcs acp_ip_funcs = {

	.name = "acp_ip",

	.early_init = acp_early_init,

	.late_init = NULL,

	.sw_init = acp_sw_init,

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+1 −3
Original line number Diff line number Diff line
@@ -793,7 +793,6 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 
				struct cgs_system_info *sys_info)

{

	CGS_FUNC_ADEV;

	struct amdgpu_cu_info cu_info;



	if (NULL == sys_info)

		return -ENODEV;
@@ -818,8 +817,7 @@ static int amdgpu_cgs_query_system_info(struct cgs_device *cgs_device, 
		sys_info->value = adev->pg_flags;

		break;

	case CGS_SYSTEM_INFO_GFX_CU_INFO:

		amdgpu_asic_get_cu_info(adev, &cu_info);

		sys_info->value = cu_info.number;

		sys_info->value = adev->gfx.cu_info.number;

		break;

	default:

		return -ENODEV;

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+48 −56
Original line number Diff line number Diff line
@@ -87,44 +87,42 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 
}



static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,

				      struct amdgpu_user_fence *uf,

				      struct drm_amdgpu_cs_chunk_fence *fence_data)

				      struct drm_amdgpu_cs_chunk_fence *data,

				      uint32_t *offset)

{

	struct drm_gem_object *gobj;

	uint32_t handle;



	handle = fence_data->handle;

	gobj = drm_gem_object_lookup(p->adev->ddev, p->filp,

				     fence_data->handle);

				     data->handle);

	if (gobj == NULL)

		return -EINVAL;



	uf->bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));

	uf->offset = fence_data->offset;



	if (amdgpu_ttm_tt_get_usermm(uf->bo->tbo.ttm)) {

		drm_gem_object_unreference_unlocked(gobj);

		return -EINVAL;

	}



	p->uf_entry.robj = amdgpu_bo_ref(uf->bo);

	p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));

	p->uf_entry.priority = 0;

	p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;

	p->uf_entry.tv.shared = true;

	p->uf_entry.user_pages = NULL;

	*offset = data->offset;



	drm_gem_object_unreference_unlocked(gobj);



	if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {

		amdgpu_bo_unref(&p->uf_entry.robj);

		return -EINVAL;

	}



	return 0;

}



int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)

{

	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;

	struct amdgpu_vm *vm = &fpriv->vm;

	union drm_amdgpu_cs *cs = data;

	uint64_t *chunk_array_user;

	uint64_t *chunk_array;

	struct amdgpu_user_fence uf = {};

	unsigned size, num_ibs = 0;

	uint32_t uf_offset = 0;

	int i;

	int ret;
@@ -199,7 +197,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
				goto free_partial_kdata;

			}



			ret = amdgpu_cs_user_fence_chunk(p, &uf, (void *)p->chunks[i].kdata);

			ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,

							 &uf_offset);

			if (ret)

				goto free_partial_kdata;
@@ -214,11 +213,14 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) 
		}

	}



	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job);

	ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);

	if (ret)

		goto free_all_kdata;



	p->job->uf = uf;

	if (p->uf_entry.robj) {

		p->job->uf_bo = amdgpu_bo_ref(p->uf_entry.robj);

		p->job->uf_offset = uf_offset;

	}



	kfree(chunk_array);

	return 0;
@@ -376,7 +378,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
	INIT_LIST_HEAD(&duplicates);

	amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);



	if (p->job->uf.bo)

	if (p->uf_entry.robj)

		list_add(&p->uf_entry.tv.head, &p->validated);



	if (need_mmap_lock)
@@ -472,6 +474,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 
		goto error_validate;



	if (p->bo_list) {

		struct amdgpu_bo *gds = p->bo_list->gds_obj;

		struct amdgpu_bo *gws = p->bo_list->gws_obj;

		struct amdgpu_bo *oa = p->bo_list->oa_obj;

		struct amdgpu_vm *vm = &fpriv->vm;

		unsigned i;
@@ -480,6 +485,19 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, 


			p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);

		}



		if (gds) {

			p->job->gds_base = amdgpu_bo_gpu_offset(gds);

			p->job->gds_size = amdgpu_bo_size(gds);

		}

		if (gws) {

			p->job->gws_base = amdgpu_bo_gpu_offset(gws);

			p->job->gws_size = amdgpu_bo_size(gws);

		}

		if (oa) {

			p->job->oa_base = amdgpu_bo_gpu_offset(oa);

			p->job->oa_size = amdgpu_bo_size(oa);

		}

	}



error_validate:
@@ -740,42 +758,15 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, 


		ib->length_dw = chunk_ib->ib_bytes / 4;

		ib->flags = chunk_ib->flags;

		ib->ctx = parser->ctx;

		j++;

	}



	/* add GDS resources to first IB */

	if (parser->bo_list) {

		struct amdgpu_bo *gds = parser->bo_list->gds_obj;

		struct amdgpu_bo *gws = parser->bo_list->gws_obj;

		struct amdgpu_bo *oa = parser->bo_list->oa_obj;

		struct amdgpu_ib *ib = &parser->job->ibs[0];



		if (gds) {

			ib->gds_base = amdgpu_bo_gpu_offset(gds);

			ib->gds_size = amdgpu_bo_size(gds);

		}

		if (gws) {

			ib->gws_base = amdgpu_bo_gpu_offset(gws);

			ib->gws_size = amdgpu_bo_size(gws);

		}

		if (oa) {

			ib->oa_base = amdgpu_bo_gpu_offset(oa);

			ib->oa_size = amdgpu_bo_size(oa);

		}

	}

	/* wrap the last IB with user fence */

	if (parser->job->uf.bo) {

		struct amdgpu_ib *ib = &parser->job->ibs[parser->job->num_ibs - 1];



	/* UVD & VCE fw doesn't support user fences */

		if (parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||

		    parser->job->ring->type == AMDGPU_RING_TYPE_VCE)

	if (parser->job->uf_bo && (

	    parser->job->ring->type == AMDGPU_RING_TYPE_UVD ||

	    parser->job->ring->type == AMDGPU_RING_TYPE_VCE))

		return -EINVAL;



		ib->user = &parser->job->uf;

	}



	return 0;

}
@@ -839,6 +830,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
			    union drm_amdgpu_cs *cs)

{

	struct amdgpu_ring *ring = p->job->ring;

	struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;

	struct fence *fence;

	struct amdgpu_job *job;

	int r;
@@ -847,8 +839,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	p->job = NULL;



	r = amd_sched_job_init(&job->base, &ring->sched,

						&p->ctx->rings[ring->idx].entity,

						amdgpu_job_timeout_func,

			       entity, amdgpu_job_timeout_func,

			       amdgpu_job_free_func,

			       p->filp, &fence);

	if (r) {
@@ -857,9 +848,10 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, 
	}



	job->owner = p->filp;

	job->ctx = entity->fence_context;

	p->fence = fence_get(fence);

	cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, fence);

	job->ibs[job->num_ibs - 1].sequence = cs->out.handle;

	job->uf_sequence = cs->out.handle;



	trace_amdgpu_cs_ioctl(job);

	amd_sched_entity_push_job(&job->base);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+12 −12
Original line number Diff line number Diff line
@@ -1196,7 +1196,7 @@ static int amdgpu_early_init(struct amdgpu_device *adev) 
				if (r == -ENOENT) {

					adev->ip_block_status[i].valid = false;

				} else if (r) {

					DRM_ERROR("early_init %d failed %d\n", i, r);

					DRM_ERROR("early_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

					return r;

				} else {

					adev->ip_block_status[i].valid = true;
@@ -1219,7 +1219,7 @@ static int amdgpu_init(struct amdgpu_device *adev) 
			continue;

		r = adev->ip_blocks[i].funcs->sw_init((void *)adev);

		if (r) {

			DRM_ERROR("sw_init %d failed %d\n", i, r);

			DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			return r;

		}

		adev->ip_block_status[i].sw = true;
@@ -1252,7 +1252,7 @@ static int amdgpu_init(struct amdgpu_device *adev) 
			continue;

		r = adev->ip_blocks[i].funcs->hw_init((void *)adev);

		if (r) {

			DRM_ERROR("hw_init %d failed %d\n", i, r);

			DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			return r;

		}

		adev->ip_block_status[i].hw = true;
@@ -1272,13 +1272,13 @@ static int amdgpu_late_init(struct amdgpu_device *adev) 
		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

								    AMD_CG_STATE_GATE);

		if (r) {

			DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);

			DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			return r;

		}

		if (adev->ip_blocks[i].funcs->late_init) {

			r = adev->ip_blocks[i].funcs->late_init((void *)adev);

			if (r) {

				DRM_ERROR("late_init %d failed %d\n", i, r);

				DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

				return r;

			}

		}
@@ -1302,13 +1302,13 @@ static int amdgpu_fini(struct amdgpu_device *adev) 
		r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

								    AMD_CG_STATE_UNGATE);

		if (r) {

			DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);

			DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			return r;

		}

		r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);

		/* XXX handle errors */

		if (r) {

			DRM_DEBUG("hw_fini %d failed %d\n", i, r);

			DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

		}

		adev->ip_block_status[i].hw = false;

	}
@@ -1319,7 +1319,7 @@ static int amdgpu_fini(struct amdgpu_device *adev) 
		r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);

		/* XXX handle errors */

		if (r) {

			DRM_DEBUG("sw_fini %d failed %d\n", i, r);

			DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

		}

		adev->ip_block_status[i].sw = false;

		adev->ip_block_status[i].valid = false;
@@ -1347,14 +1347,14 @@ static int amdgpu_suspend(struct amdgpu_device *adev) 
			r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,

									    AMD_CG_STATE_UNGATE);

			if (r) {

				DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);

				DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			}

		}

		/* XXX handle errors */

		r = adev->ip_blocks[i].funcs->suspend(adev);

		/* XXX handle errors */

		if (r) {

			DRM_ERROR("suspend %d failed %d\n", i, r);

			DRM_ERROR("suspend of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

		}

	}
@@ -1370,7 +1370,7 @@ static int amdgpu_resume(struct amdgpu_device *adev) 
			continue;

		r = adev->ip_blocks[i].funcs->resume(adev);

		if (r) {

			DRM_ERROR("resume %d failed %d\n", i, r);

			DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].funcs->name, r);

			return r;

		}

	}