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Commit 7ccc83b0 authored by Christian Lamparter's avatar Christian Lamparter Committed by John W. Linville
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carl9170: fix timekeeping for HW_COUNTER firmwares



AR9170_PWR_REG_PLL_ADDAC is used to set the main clock
divisor which affects the AHB/CPU speed. Because this
would interfere with the firmware internal timekeeping,
the function has to be moved into the firmware.

Signed-off-by: default avatarChristian Lamparter <chunkeey@googlemail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent bfe2ed8f
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+1 −0
Original line number Diff line number Diff line
@@ -282,6 +282,7 @@ struct ar9170 {
		bool rx_stream;
		bool tx_stream;
		bool rx_filter;
		bool hw_counters;
		unsigned int mem_blocks;
		unsigned int mem_block_size;
		unsigned int rx_size;
+3 −0
Original line number Diff line number Diff line
@@ -266,6 +266,9 @@ static int carl9170_fw(struct ar9170 *ar, const __u8 *data, size_t len)
			FIF_PROMISC_IN_BSS;
	}

	if (SUPP(CARL9170FW_HW_COUNTERS))
		ar->fw.hw_counters = true;

	if (SUPP(CARL9170FW_WOL))
		device_set_wakeup_enable(&ar->udev->dev, true);

+4 −5
Original line number Diff line number Diff line
@@ -578,11 +578,10 @@ static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
	if (err)
		return err;

	/* XXX: remove magic! */
	if (is_2ghz)
		err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163);
	else
		err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143);
	if (!ar->fw.hw_counters) {
		err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC,
					 is_2ghz ? 0x5163 : 0x5143);
	}

	return err;
}