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Commit 7c114e86 authored by Rajneesh Bhardwaj's avatar Rajneesh Bhardwaj Committed by Greg Kroah-Hartman
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platform/x86: intel_pmc_core: Fix PCH IP sts reading 



[ Upstream commit 0e68eeea9894feeba2edf7ec63e4551b87f39621 ]

A previous commit "platform/x86: intel_pmc_core: Make the driver PCH
family agnostic <c977b98b>" provided
better abstraction to this driver but has some fundamental issues.

e.g. the following condition

for (index = 0; index < pmcdev->map->ppfear_buckets &&
	index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)

is wrong because for CNL, PPFEAR_MAX_NUM_ENTRIES is hardcoded as 5 which
is _wrong_ and even though ppfear_buckets is 8, the loop fails to read
all eight registers needed for CNL PCH i.e. PPFEAR0 and PPFEAR1. This
patch refactors the pfear show logic to correctly read PCH IP power
gating status for Cannonlake and beyond.

Cc: "David E. Box" <david.e.box@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Fixes: c977b98b ("platform/x86: intel_pmc_core: Make the driver PCH family agnostic")
Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent b9f257e2

drivers/platform/x86/intel_pmc_core.c

+2 −1
Original line number Diff line number Diff line
@@ -333,7 +333,8 @@ static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused) 
	     index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)

		pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);



	for (index = 0; map[index].name; index++)

	for (index = 0; map[index].name &&

	     index < pmcdev->map->ppfear_buckets * 8; index++)

		pmc_core_display_map(s, index, pf_regs[index / 8], map);



	return 0;

drivers/platform/x86/intel_pmc_core.h

+1 −1
Original line number Diff line number Diff line
@@ -39,7 +39,7 @@ 
#define SPT_PMC_SLP_S0_RES_COUNTER_STEP		0x64

#define PMC_BASE_ADDR_MASK			~(SPT_PMC_MMIO_REG_LEN - 1)

#define MTPMC_MASK				0xffff0000

#define PPFEAR_MAX_NUM_ENTRIES			5

#define PPFEAR_MAX_NUM_ENTRIES			12

#define SPT_PPFEAR_NUM_ENTRIES			5

#define SPT_PMC_READ_DISABLE_BIT		0x16

#define SPT_PMC_MSG_FULL_STS_BIT		0x18