Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux-2.6

OMAP GPIO controller bindings

Required properties:

- compatible:

  - "ti,omap2-gpio" for OMAP2 controllers

  - "ti,omap3-gpio" for OMAP3 controllers

  - "ti,omap4-gpio" for OMAP4 controllers

- #gpio-cells : Should be two.

  - first cell is the pin number

  - second cell is used to specify optional parameters (unused)

- gpio-controller : Marks the device node as a GPIO controller.

- #interrupt-cells : Should be 2.

- interrupt-controller: Mark the device node as an interrupt controller

  The first cell is the GPIO number.

  The second cell is used to specify flags:

    bits[3:0] trigger type and level flags:

      1 = low-to-high edge triggered.

      2 = high-to-low edge triggered.

      4 = active high level-sensitive.

      8 = active low level-sensitive.

OMAP specific properties:

- ti,hwmods: Name of the hwmod associated to the GPIO:

  "gpio<X>", <X> being the 1-based instance number from the HW spec

Example:

gpio4: gpio4 {

    compatible = "ti,omap4-gpio";

    ti,hwmods = "gpio4";

    #gpio-cells = <2>;

    gpio-controller;

    #interrupt-cells = <2>;

    interrupt-controller;

};

GPIO controller on CE4100 / Sodaville SoCs

==========================================

The bindings for CE4100's GPIO controller match the generic description

which is covered by the gpio.txt file in this folder.

The only additional property is the intel,muxctl property which holds the

value which is written into the MUXCNTL register.

There is no compatible property for now because the driver is probed via

PCI id (vendor 0x8086 device 0x2e67).

The interrupt specifier consists of two cells encoded as follows:

 - <1st cell>: The interrupt-number that identifies the interrupt source.

 - <2nd cell>: The level-sense information, encoded as follows:

		4 - active high level-sensitive

		8 - active low level-sensitive

Example of the GPIO device and one user:

	pcigpio: gpio@b,1 {

			/* two cells for GPIO and interrupt */

			#gpio-cells = <2>;

			#interrupt-cells = <2>;

			compatible = "pci8086,2e67.2",

					   "pci8086,2e67",

					   "pciclassff0000",

					   "pciclassff00";

			reg = <0x15900 0x0 0x0 0x0 0x0>;

			/* Interrupt line of the gpio device */

			interrupts = <15 1>;

			/* It is an interrupt and GPIO controller itself */

			interrupt-controller;

			gpio-controller;

			intel,muxctl = <0>;

	};

	testuser@20 {

			compatible = "example,testuser";

			/* User the 11th GPIO line as an active high triggered

			 * level interrupt

			 */

			interrupts = <11 8>;

			interrupt-parent = <&pcigpio>;

			/* Use this GPIO also with the gpio functions */

			gpios = <&pcigpio 11 0>;

	};

power management, such as by powering down unused chip sectors and, more

easily, gating off unused clocks.

Note that requesting a GPIO does NOT cause it to be configured in any

way; it just marks that GPIO as in use.  Separate code must handle any

pin setup (e.g. controlling which pin the GPIO uses, pullup/pulldown).

For GPIOs that use pins known to the pinctrl subsystem, that subsystem should

be informed of their use; a gpiolib driver's .request() operation may call

pinctrl_request_gpio(), and a gpiolib driver's .free() operation may call

pinctrl_free_gpio(). The pinctrl subsystem allows a pinctrl_request_gpio()

to succeed concurrently with a pin or pingroup being "owned" by a device for

pin multiplexing.

Any programming of pin multiplexing hardware that is needed to route the

GPIO signal to the appropriate pin should occur within a GPIO driver's

.direction_input() or .direction_output() operations, and occur after any

setup of an output GPIO's value. This allows a glitch-free migration from a

pin's special function to GPIO. This is sometimes required when using a GPIO

to implement a workaround on signals typically driven by a non-GPIO HW block.

Some platforms allow some or all GPIO signals to be routed to different pins.

Similarly, other aspects of the GPIO or pin may need to be configured, such as

pullup/pulldown. Platform software should arrange that any such details are

configured prior to gpio_request() being called for those GPIOs, e.g. using

the pinctrl subsystem's mapping table, so that GPIO users need not be aware

of these details.

Also note that it's your responsibility to have stopped using a GPIO

before you free it.

	* GPIOF_INIT_LOW	- as output, set initial level to LOW

	* GPIOF_INIT_HIGH	- as output, set initial level to HIGH

	* GPIOF_OPEN_DRAIN	- gpio pin is open drain type.

	* GPIOF_OPEN_SOURCE	- gpio pin is open source type.

since GPIOF_INIT_* are only valid when configured as output, so group valid

combinations as:

	* GPIOF_OUT_INIT_LOW	- configured as output, initial level LOW

	* GPIOF_OUT_INIT_HIGH	- configured as output, initial level HIGH

In the future, these flags can be extended to support more properties such

as open-drain status.

When setting the flag as GPIOF_OPEN_DRAIN then it will assume that pins is

open drain type. Such pins will not be driven to 1 in output mode. It is

require to connect pull-up on such pins. By enabling this flag, gpio lib will

make the direction to input when it is asked to set value of 1 in output mode

to make the pin HIGH. The pin is make to LOW by driving value 0 in output mode.

When setting the flag as GPIOF_OPEN_SOURCE then it will assume that pins is

open source type. Such pins will not be driven to 0 in output mode. It is

require to connect pull-down on such pin. By enabling this flag, gpio lib will

make the direction to input when it is asked to set value of 0 in output mode

to make the pin LOW. The pin is make to HIGH by driving value 1 in output mode.

In the future, these flags can be extended to support more properties.

Further more, to ease the claim/release of multiple GPIOs, 'struct gpio' is

introduced to encapsulate all three fields as:

extern void omap_set_gpio_debounce_time(int gpio, int enable);

/*-------------------------------------------------------------------------*/

/* Wrappers for "new style" GPIO calls, using the new infrastructure

/*

 * Wrappers for "new style" GPIO calls, using the new infrastructure

 * which lets us plug in FPGA, I2C, and other implementations.

 * *

 *

 * The original OMAP-specific calls should eventually be removed.

 */

#include <linux/errno.h>

#include <asm-generic/gpio.h>

static inline int irq_to_gpio(unsigned irq)

{

	int tmp;

	/* omap1 SOC mpuio */

	if (cpu_class_is_omap1() && (irq < (IH_MPUIO_BASE + 16)))

		return (irq - IH_MPUIO_BASE) + OMAP_MAX_GPIO_LINES;

	/* SOC gpio */

	tmp = irq - IH_GPIO_BASE;

	if (tmp < OMAP_MAX_GPIO_LINES)

		return tmp;

	/* we don't supply reverse mappings for non-SOC gpios */

	return -EIO;

}

#endif

					interrupts = <14 1>;

				};

				gpio@b,1 {

				pcigpio: gpio@b,1 {

					#gpio-cells = <2>;

					#interrupt-cells = <2>;

					compatible = "pci8086,2e67.2",

						   "pci8086,2e67",

						   "pciclassff0000",

						   "pciclassff00";

					#gpio-cells = <2>;

					reg = <0x15900 0x0 0x0 0x0 0x0>;

					interrupts = <15 1>;

					interrupt-controller;

					gpio-controller;

					intel,muxctl = <0>;

				};

				i2c-controller@b,2 {