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Commit 7b6ba9ea authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: update GC 9.1 raven specific golden settings 



Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 01b5cc36

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+7 −4
Original line number Diff line number Diff line
@@ -163,14 +163,17 @@ static const u32 golden_settings_gc_9_1[] = 


static const u32 golden_settings_gc_9_1_rv1[] =

{

	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x26013042,

	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x26013042,

	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x00048000,

	SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,

	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,

	SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,

	SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,

	SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,

	SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,

	SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800

};



#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042

#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x26013042

#define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042



static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);

static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);