Loading drivers/mmc/host/dw_mmc-rockchip.c +0 −8 Original line number Diff line number Diff line Loading @@ -239,20 +239,12 @@ static int dw_mci_rockchip_init(struct dw_mci *host) return 0; } /* Common capabilities of RK3288 SoC */ static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { MMC_CAP_RUNTIME_RESUME, /* emmc */ MMC_CAP_RUNTIME_RESUME, /* sdmmc */ MMC_CAP_RUNTIME_RESUME, /* sdio0 */ MMC_CAP_RUNTIME_RESUME, /* sdio1 */ }; static const struct dw_mci_drv_data rk2928_drv_data = { .prepare_command = dw_mci_rockchip_prepare_command, .init = dw_mci_rockchip_init, }; static const struct dw_mci_drv_data rk3288_drv_data = { .caps = dw_mci_rk3288_dwmmc_caps, .prepare_command = dw_mci_rockchip_prepare_command, .set_ios = dw_mci_rk3288_set_ios, .execute_tuning = dw_mci_rk3288_execute_tuning, Loading drivers/mmc/host/mtk-sd.c +0 −1 Original line number Diff line number Diff line Loading @@ -1543,7 +1543,6 @@ static int msdc_drv_probe(struct platform_device *pdev) mmc->f_min = host->src_clk_freq / (4 * 255); mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; mmc->caps |= MMC_CAP_RUNTIME_RESUME; /* MMC core transfer sizes tunable parameters */ mmc->max_segs = MAX_BD_NUM; mmc->max_seg_size = BDMA_DESC_BUFLEN; Loading include/linux/mmc/host.h +0 −1 Original line number Diff line number Diff line Loading @@ -259,7 +259,6 @@ struct mmc_host { #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ #define MMC_CAP_RUNTIME_RESUME (1 << 20) /* Resume at runtime_resume. */ #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ Loading Loading
drivers/mmc/host/dw_mmc-rockchip.c +0 −8 Original line number Diff line number Diff line Loading @@ -239,20 +239,12 @@ static int dw_mci_rockchip_init(struct dw_mci *host) return 0; } /* Common capabilities of RK3288 SoC */ static unsigned long dw_mci_rk3288_dwmmc_caps[4] = { MMC_CAP_RUNTIME_RESUME, /* emmc */ MMC_CAP_RUNTIME_RESUME, /* sdmmc */ MMC_CAP_RUNTIME_RESUME, /* sdio0 */ MMC_CAP_RUNTIME_RESUME, /* sdio1 */ }; static const struct dw_mci_drv_data rk2928_drv_data = { .prepare_command = dw_mci_rockchip_prepare_command, .init = dw_mci_rockchip_init, }; static const struct dw_mci_drv_data rk3288_drv_data = { .caps = dw_mci_rk3288_dwmmc_caps, .prepare_command = dw_mci_rockchip_prepare_command, .set_ios = dw_mci_rk3288_set_ios, .execute_tuning = dw_mci_rk3288_execute_tuning, Loading
drivers/mmc/host/mtk-sd.c +0 −1 Original line number Diff line number Diff line Loading @@ -1543,7 +1543,6 @@ static int msdc_drv_probe(struct platform_device *pdev) mmc->f_min = host->src_clk_freq / (4 * 255); mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; mmc->caps |= MMC_CAP_RUNTIME_RESUME; /* MMC core transfer sizes tunable parameters */ mmc->max_segs = MAX_BD_NUM; mmc->max_seg_size = BDMA_DESC_BUFLEN; Loading
include/linux/mmc/host.h +0 −1 Original line number Diff line number Diff line Loading @@ -259,7 +259,6 @@ struct mmc_host { #define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */ #define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */ #define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */ #define MMC_CAP_RUNTIME_RESUME (1 << 20) /* Resume at runtime_resume. */ #define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */ #define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */ #define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */ Loading