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Commit 7aac405e authored by Robin Murphy's avatar Robin Murphy Committed by Catalin Marinas
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arm64: Expose DC CVAP to userspace 



The ARMv8.2-DCPoP feature introduces persistent memory support to the
architecture, by defining a point of persistence in the memory
hierarchy, and a corresponding cache maintenance operation, DC CVAP.
Expose the support via HWCAP and MRS emulation.

Reviewed-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarRobin Murphy <robin.murphy@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent d46befef

Documentation/arm64/cpu-feature-registers.txt

+2 −0
Original line number Diff line number Diff line
@@ -179,6 +179,8 @@ infrastructure: 
     | FCMA                         | [19-16] |    y    |

     |--------------------------------------------------|

     | JSCVT                        | [15-12] |    y    |

     |--------------------------------------------------|

     | DPB                          | [3-0]   |    y    |

     x--------------------------------------------------x



Appendix I: Example

arch/arm64/include/asm/sysreg.h

+1 −0
Original line number Diff line number Diff line
@@ -329,6 +329,7 @@ 
#define ID_AA64ISAR1_LRCPC_SHIFT	20

#define ID_AA64ISAR1_FCMA_SHIFT		16

#define ID_AA64ISAR1_JSCVT_SHIFT	12

#define ID_AA64ISAR1_DPB_SHIFT		0



/* id_aa64pfr0 */

#define ID_AA64PFR0_GIC_SHIFT		24

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -35,5 +35,6 @@ 
#define HWCAP_JSCVT		(1 << 13)

#define HWCAP_FCMA		(1 << 14)

#define HWCAP_LRCPC		(1 << 15)

#define HWCAP_DCPOP		(1 << 16)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -120,6 +120,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 
	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_DPB_SHIFT, 4, 0),

	ARM64_FTR_END,

};
@@ -916,6 +917,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),

	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),

	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -68,6 +68,7 @@ static const char *const hwcap_str[] = { 
	"jscvt",

	"fcma",

	"lrcpc",

	"dcpop",

	NULL

};