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Commit 7a39a9d4 authored by Daniel Kurtz's avatar Daniel Kurtz Committed by Daniel Vetter
Browse files

drm/i915/intel_i2c: use double-buffered writes 



The GMBUS controller GMBUS3 register is double-buffered.  Take advantage
of this  by writing two 4-byte words before the first wait for HW_RDY.
This helps keep the GMBUS controller from becoming idle during long writes.

In fact, during experiments using the GMBUS interrupts, the HW_RDY
interrupt would only trigger for transactions >4 bytes after 2 writes
to GMBUS3.

Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 26883c31

drivers/gpu/drm/i915/intel_i2c.c

+7 −7
Original line number Diff line number Diff line
@@ -262,13 +262,6 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 
		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);

	POSTING_READ(GMBUS2 + reg_offset);

	while (len) {

		if (wait_for(I915_READ(GMBUS2 + reg_offset) &

			     (GMBUS_SATOER | GMBUS_HW_RDY),

			     50))

			return -ETIMEDOUT;

		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

			return -ENXIO;



		val = loop = 0;

		do {

			val |= *buf++ << (8 * loop);
@@ -276,6 +269,13 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 


		I915_WRITE(GMBUS3 + reg_offset, val);

		POSTING_READ(GMBUS2 + reg_offset);



		if (wait_for(I915_READ(GMBUS2 + reg_offset) &

			     (GMBUS_SATOER | GMBUS_HW_RDY),

			     50))

			return -ETIMEDOUT;

		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)

			return -ENXIO;

	}

	return 0;

}