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Commit 79e87830 authored by Michal Simek's avatar Michal Simek
Browse files

microblaze: Implement flush_dcache_page macro 



flush_dcache_page macro is necessary to implement for
JFFS2 rootfs support on WB system.

Signed-off-by: default avatarMichal Simek <monstr@monstr.eu>
parent af58ed85

arch/microblaze/include/asm/cacheflush.h

+10 −4
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


/* Somebody depends on this; sigh... */

#include <linux/mm.h>

#include <linux/io.h>



/* Look at Documentation/cachetlb.txt */
@@ -60,7 +61,6 @@ void microblaze_cache_init(void); 
#define invalidate_icache()				mbc->iin();

#define invalidate_icache_range(start, end)		mbc->iinr(start, end);





#define flush_icache_user_range(vma, pg, adr, len)	flush_icache();

#define flush_icache_page(vma, pg)			do { } while (0)
@@ -72,9 +72,15 @@ void microblaze_cache_init(void); 
#define flush_dcache()					mbc->dfl();

#define flush_dcache_range(start, end)			mbc->dflr(start, end);



#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0

/* D-cache aliasing problem can't happen - cache is between MMU and ram */

#define flush_dcache_page(page)			do { } while (0)

#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1

/* MS: We have to implement it because of rootfs-jffs2 issue on WB */

#define flush_dcache_page(page) \

do { \

	unsigned long addr = (unsigned long) page_address(page); /* virtual */ \

	addr = (u32)virt_to_phys((void *)addr); \

	flush_dcache_range((unsigned) (addr), (unsigned) (addr) + PAGE_SIZE); \

} while (0);



#define flush_dcache_mmap_lock(mapping)		do { } while (0)

#define flush_dcache_mmap_unlock(mapping)	do { } while (0)