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Commit 7963f58c authored by Masahiro Yamada's avatar Masahiro Yamada Committed by Boris Brezillon
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mtd: nand: denali: fix setup_data_interface to meet tCCS delay 



The WE_2_RE register specifies the number of clock cycles inserted
between the rising edge of #WE and the falling edge of #RE.

The current setup_data_interface implementation takes care of tWHR,
but tCCS is missing.  Wait for max(tCSS, tWHR) to meet the spec.

With setup_data_interface() properly programmed, the Denali NAND
controller can observe the timing, so NAND_WAIT_TCCS flag is unneeded.
Clarify this in the comment block.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
parent 263c68af

drivers/mtd/nand/denali.c

+8 −2
Original line number Diff line number Diff line
@@ -1004,8 +1004,14 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, 
	tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);

	iowrite32(tmp, denali->reg + RE_2_RE);



	/* tWHR -> WE_2_RE */

	we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk);

	/*

	 * tCCS, tWHR -> WE_2_RE

	 *

	 * With WE_2_RE properly set, the Denali controller automatically takes

	 * care of the delay; the driver need not set NAND_WAIT_TCCS.

	 */

	we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),

			       t_clk);

	we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);



	tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);