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Commit 7934d69a authored Jan 21, 2015 by Sudeep Holla Committed by Arnd Bergmann Feb 25, 2015

arm64: Add L2 cache topology to ARM Ltd boards/models



Commit 5d425c18 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.

This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

parent c517d838

arch/arm64/boot/dts/arm/foundation-v8.dts

+8 −0

Original line number	Diff line number	Diff line
		@@ -34,6 +34,7 @@
		reg = <0x0 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@1 {
		device_type = "cpu";
		@@ -41,6 +42,7 @@
		reg = <0x0 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@2 {
		device_type = "cpu";
		@@ -48,6 +50,7 @@
		reg = <0x0 0x2>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@3 {
		device_type = "cpu";
		@@ -55,6 +58,11 @@
		reg = <0x0 0x3>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
		compatible = "cache";
		};
		};

arch/arm64/boot/dts/arm/juno.dts

+14 −0

Original line number	Diff line number	Diff line
		@@ -39,6 +39,7 @@
		reg = <0x0 0x0>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A57_L2>;
		};

		A57_1: cpu@1 {
		@@ -46,6 +47,7 @@
		reg = <0x0 0x1>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A57_L2>;
		};

		A53_0: cpu@100 {
		@@ -53,6 +55,7 @@
		reg = <0x0 0x100>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		};

		A53_1: cpu@101 {
		@@ -60,6 +63,7 @@
		reg = <0x0 0x101>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		};

		A53_2: cpu@102 {
		@@ -67,6 +71,7 @@
		reg = <0x0 0x102>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		};

		A53_3: cpu@103 {
		@@ -74,6 +79,15 @@
		reg = <0x0 0x103>;
		device_type = "cpu";
		enable-method = "psci";
		next-level-cache = <&A53_L2>;
		};

		A57_L2: l2-cache0 {
		compatible = "cache";
		};

		A53_L2: l2-cache1 {
		compatible = "cache";
		};
		};

arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts

+8 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,7 @@
		reg = <0x0 0x0>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@1 {
		device_type = "cpu";
		@@ -44,6 +45,7 @@
		reg = <0x0 0x1>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@2 {
		device_type = "cpu";
		@@ -51,6 +53,7 @@
		reg = <0x0 0x2>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};
		cpu@3 {
		device_type = "cpu";
		@@ -58,6 +61,11 @@
		reg = <0x0 0x3>;
		enable-method = "spin-table";
		cpu-release-addr = <0x0 0x8000fff8>;
		next-level-cache = <&L2_0>;
		};

		L2_0: l2-cache0 {
		compatible = "cache";
		};
		};