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Commit 78145a95 authored by Ricardo Neri's avatar Ricardo Neri Committed by Tomi Valkeinen
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OMAPDSS: HDMI: OMAP4: Complete dumping of core registers 



Add missing register entries when dumping the core.

Signed-off-by: default avatarRicardo Neri <ricardo.neri@ti.com>
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent 46c4a755

drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

+46 −1
Original line number Diff line number Diff line
@@ -911,6 +911,7 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) 
	DUMPCORE(HDMI_CORE_SYS_SRST);

	DUMPCORE(HDMI_CORE_SYS_SYS_CTRL1);

	DUMPCORE(HDMI_CORE_SYS_SYS_STAT);

	DUMPCORE(HDMI_CORE_SYS_SYS_CTRL3);

	DUMPCORE(HDMI_CORE_SYS_DE_DLY);

	DUMPCORE(HDMI_CORE_SYS_DE_CTRL);

	DUMPCORE(HDMI_CORE_SYS_DE_TOP);
@@ -918,14 +919,58 @@ void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s) 
	DUMPCORE(HDMI_CORE_SYS_DE_CNTH);

	DUMPCORE(HDMI_CORE_SYS_DE_LINL);

	DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);

	DUMPCORE(HDMI_CORE_SYS_HRES_L);

	DUMPCORE(HDMI_CORE_SYS_HRES_H);

	DUMPCORE(HDMI_CORE_SYS_VRES_L);

	DUMPCORE(HDMI_CORE_SYS_VRES_H);

	DUMPCORE(HDMI_CORE_SYS_IADJUST);

	DUMPCORE(HDMI_CORE_SYS_POLDETECT);

	DUMPCORE(HDMI_CORE_SYS_HWIDTH1);

	DUMPCORE(HDMI_CORE_SYS_HWIDTH2);

	DUMPCORE(HDMI_CORE_SYS_VWIDTH);

	DUMPCORE(HDMI_CORE_SYS_VID_CTRL);

	DUMPCORE(HDMI_CORE_SYS_VID_ACEN);

	DUMPCORE(HDMI_CORE_SYS_VID_MODE);

	DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);

	DUMPCORE(HDMI_CORE_SYS_VID_BLANK3);

	DUMPCORE(HDMI_CORE_SYS_VID_BLANK1);

	DUMPCORE(HDMI_CORE_SYS_DC_HEADER);

	DUMPCORE(HDMI_CORE_SYS_VID_DITHER);

	DUMPCORE(HDMI_CORE_SYS_RGB2XVYCC_CT);

	DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_R2Y_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_G2Y_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_B2Y_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_R2CB_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_G2CB_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_B2CB_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_R2CR_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_G2CR_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_LOW);

	DUMPCORE(HDMI_CORE_SYS_B2CR_COEFF_UP);

	DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_LOW);

	DUMPCORE(HDMI_CORE_SYS_RGB_OFFSET_UP);

	DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_LOW);

	DUMPCORE(HDMI_CORE_SYS_Y_OFFSET_UP);

	DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_LOW);

	DUMPCORE(HDMI_CORE_SYS_CBCR_OFFSET_UP);

	DUMPCORE(HDMI_CORE_SYS_INTR_STATE);

	DUMPCORE(HDMI_CORE_SYS_INTR1);

	DUMPCORE(HDMI_CORE_SYS_INTR2);

	DUMPCORE(HDMI_CORE_SYS_INTR3);

	DUMPCORE(HDMI_CORE_SYS_INTR4);

	DUMPCORE(HDMI_CORE_SYS_UMASK1);

	DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK1);

	DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK2);

	DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK3);

	DUMPCORE(HDMI_CORE_SYS_INTR_UNMASK4);

	DUMPCORE(HDMI_CORE_SYS_INTR_CTRL);

	DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);



	DUMPCORE(HDMI_CORE_DDC_ADDR);