ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits

Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>