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Unverified Commit 77bdb587 authored by Andrew F. Davis's avatar Andrew F. Davis Committed by Mark Brown
Browse files

ASoC: tlv320aic32x4: Use correct shift definition for DATALEN bits 



Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.

Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 4483521d

sound/soc/codecs/tlv320aic32x4.c

+8 −3
Original line number Original line Diff line number Diff line
@@ -738,15 +738,20 @@ static int aic32x4_hw_params(struct snd_pcm_substream *substream, 
	data = data & ~(3 << 4);

	data = data & ~(3 << 4);

	switch (params_width(params)) {

	switch (params_width(params)) {

	case 16:

	case 16:

		data |= (AIC32X4_WORD_LEN_16BITS <<

			 AIC32X4_IFACE1_DATALEN_SHIFT);

		break;

		break;

	case 20:

	case 20:

		data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);

		data |= (AIC32X4_WORD_LEN_20BITS <<

			 AIC32X4_IFACE1_DATALEN_SHIFT);

		break;

		break;

	case 24:

	case 24:

		data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);

		data |= (AIC32X4_WORD_LEN_24BITS <<

			 AIC32X4_IFACE1_DATALEN_SHIFT);

		break;

		break;

	case 32:

	case 32:

		data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);

		data |= (AIC32X4_WORD_LEN_32BITS <<

			 AIC32X4_IFACE1_DATALEN_SHIFT);

		break;

		break;

	}

	}

	snd_soc_write(codec, AIC32X4_IFACE1, data);

	snd_soc_write(codec, AIC32X4_IFACE1, data);